Timing issue (flash, GPIO, wait states)

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by jsl123 on Thu Oct 10 03:31:08 MST 2013

First please have a look at the first picture. It shows the status on a GPIO pin for a 30MHz configured LPC810.
(Just added the "raw" files since the resolution was too bad...)

This is the result of the following code:

while (1) {

in complete absence of interrupts and/or timers
which results in the following assembler:

  24:   22a0            movs    r2, #160        ; 0xa0
  26:   0612            lsls    r2, r2, #24
  28:   2088            movs    r0, #136        ; 0x88
  2a:   0180            lsls    r0, r0, #6
  2c:   2304            movs    r3, #4
  2e:   218a            movs    r1, #138        ; 0x8a
  30:   0189            lsls    r1, r1, #6
  32:   5013            str     r3, [r2, r0]
  34:   5053            str     r3, [r2, r1]
  36:   5013            str     r3, [r2, r0]
  38:   5053            str     r3, [r2, r1]
  3a:   5013            str     r3, [r2, r0]
  3c:   5053            str     r3, [r2, r1]
  3e:   5013            str     r3, [r2, r0]
  40:   5053            str     r3, [r2, r1]
  42:   e7f6            b.n     32 <main+0x32>

That looks reasonable... :-)

You can find the groups of 4 and in between there is the branch.
But what makes me wonder is the difference between the "set time" (70ns) and the "clear time" (30ns)! (It's not 33.3ns because of the limited resolution of my LA. :)

If it where caching or other internal artefacts, I would perhaps assume a delay on the *first* "set" but not on later ones. But here every "set" is "long" i.e 2 cycles and every "clear" is one cycle.

Only to be complete. The second image shows the same for the internal PLL and the dividers setup to deliver 24MHz.
So it's the same here...

Does anyone have any explanation for this?

Thanks for reading! Salut,