LPC8xx USART in slave synchronous requires three dummy clock to start Tx

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by S.Kojima on Wed Jun 08 21:26:10 MST 2016
Dear fellows,

I'm trying to use USART in slave synchrounous mode for Tx, but not in success yet....
I'm using it with CTRL.CC=0 setting.
I believe that Master should supply exact number of clock pulses as frame format setting is made.
My MASTER Rx device connected externally generates exact number of clock pulses until STOP bit.
e.g. for 8E1 setting, 8bit, Start, Stop and even-parity --> Eleven pulses.

It seems ,,,,,
extra three clock pulses are ALWAYS required for LPC8xx USART Tx to make it feed the signal level of START bit, which is "L".

Is this behavior an intended one as USART's design spec ?