lpcware

Suddenly unable to debug

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by wmeitzler on Thu Feb 25 15:55:12 MST 2016
I've lost communication with my '822-based project today, and can't regain debug access. I've had debug access on the board in the past, and the problem persists across several samples of the board. Debug logs are as follows:

Quote:
LPCXpresso Debug Driver v7.9 (Jul 23 2015 14:20:04 - crt_emu_cm3_gen build 244)
Emu(0): Connected&Reset. CpuID: 410CC600. Info: HID64HS12
Debug protocol: SWD Frequency 3000 KHz. RTCK: Disabled. Vector catch: Enabled.
loaded v.2 On-chip Flash Memory C:\nxp\LPCXpresso_7.9.0_455\lpcxpresso\bin\Flash\LPC800_16.cfx
image 'LPC800 (16K) Jul 15 2015 11:49:51'
Connected: was_reset=true. was_stopped=true
LPCXpresso Free License - Download limit is 256K
Writing 9464 bytes to address 0x00000000 in Flash
Erased/Wrote page  0-9 with 9464 bytes in 343msec
Flash Write Done
Flash Program Summary: 9464 bytes in 0.34 seconds (26.95 KB/sec)
Stopped (Was Reset)  [Reset from Unknown]
Stopped: Halt



Quote:

GNU gdb (GNU Tools for ARM Embedded Processors) 7.8.0.20150604-cvs
Copyright (C) 2014 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
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Type "show configuration" for configuration details.
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0x1fff0008 in ?? ()
Ps: (  0) at 00000000: 0 bytes - 0/9464
Ps: ( 10) at 00000000: 1024 bytes - 1024/9464
Ps: ( 21) at 00000400: 1024 bytes - 2048/9464
Ps: ( 32) at 00000800: 1024 bytes - 3072/9464
Ps: ( 43) at 00000C00: 1024 bytes - 4096/9464
Ps: ( 54) at 00001000: 1024 bytes - 5120/9464
Ps: ( 64) at 00001400: 1024 bytes - 6144/9464
Ps: ( 75) at 00001800: 1024 bytes - 7168/9464
Ps: ( 86) at 00001C00: 1024 bytes - 8192/9464
Ps: ( 97) at 00002000: 1024 bytes - 9216/9464
Ps: (108) at 00002400: 1024 bytes - 10240/9464
Nc: Progress meter completed at over 100% (10240/9464 bytes)
Warning: the current language does not match this frame.
Note: automatically using hardware breakpoints for read-only addresses.



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