#include "chip.h" /****************************************************************************** * Defines *****************************************************************************/ #define INTERRUPT 1 #defineDMA1 #define SPI_BUFFER_SIZE 64 /****************************************************************************** * Global Variables *****************************************************************************/ static uint16_t txBuf[SPI_BUFFER_SIZE]; static uint16_t rxBuf[SPI_BUFFER_SIZE]; static SPI_DATA_SETUP_T tx0Setup; /****************************************************************************** * Routines *****************************************************************************/ void SPI0_IRQHandler(void) { // Disable SPI0 Interrupts Chip_SPI_Int_Cmd(LPC_SPI0, SPI_INTENSET_TXDYEN | SPI_INTENSET_RXDYEN | SPI_INTENSET_RXOVEN | SPI_INTENSET_TXUREN, DISABLE); if(tx0Setup.TxCnt < tx0Setup.Length) { Chip_SPI_Int_RWFrames(LPC_SPI0,&tx0Setup); Chip_SPI_Int_Cmd(LPC_SPI0, SPI_INTENSET_TXDYEN | SPI_INTENSET_RXDYEN | SPI_INTENSET_RXOVEN | SPI_INTENSET_TXUREN, ENABLE); } // Get status flags uint32_t status = Chip_SPI_GetStatus(LPC_SPI0); // Clear status flags Chip_SPI_ClearStatus(LPC_SPI0, status); } static void Init_SPI_PinMux(void) { // Enable the clock for the switch matrix controller Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM); // Assign a movable pin functions to a physical pins Chip_SWM_MovablePinAssign(SWM_SPI0_SCK_IO, 16); Chip_SWM_MovablePinAssign(SWM_SPI0_MOSI_IO, 27); Chip_SWM_MovablePinAssign(SWM_SPI0_MISO_IO, 26); Chip_SWM_MovablePinAssign(SWM_SPI0_SSEL0_IO, 15); // Disable the clock for the switch matrix controller Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM); } /****************************************************************************** * Start Routine *****************************************************************************/ int main(void) { volatile static int i = 0 ; // Read clock settings and update SystemCoreClock variable SystemCoreClockUpdate(); // Setup buffers for(i=0; i<SPI_BUFFER_SIZE; i++) { txBuf = i+1; rxBuf = 0; } // Initialize SPI Init_SPI_PinMux(); Chip_SPI_Init(LPC_SPI0); LPC_SPI0->CFG = (SPI_MODE_MASTER | SPI_CLOCK_CPHA0_CPOL0 | SPI_DATA_MSB_FIRST | SPI_SSEL_ACTIVE_LO); Chip_SPI_Enable(LPC_SPI0); // Initialize DMA #if(DMA) Chip_DMA_Init(LPC_DMA); Chip_DMA_Enable(LPC_DMA); Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table)); Chip_DMA_SetupChannelConfig(LPC_DMA, DMAREQ_SPI0_TX, (DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(3))); Chip_DMA_Table[DMAREQ_SPI0_TX].source = DMA_ADDR(&txBuf[SPI_BUFFER_SIZE-1]); Chip_DMA_Table[DMAREQ_SPI0_TX].dest = DMA_ADDR(&LPC_SPI0->TXDAT); Chip_DMA_Table[DMAREQ_SPI0_TX].next = DMA_ADDR(0); Chip_DMA_Table[DMAREQ_SPI0_TX].xfercfg= DMA_XFERCFG_CFGVALID | DMA_XFERCFG_SWTRIG | DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 | DMA_XFERCFG_DSTINC_0 | DMA_XFERCFG_XFERCOUNT(SPI_BUFFER_SIZE); // Setup transfer descriptor and validate it Chip_DMA_SetupTranChannel(LPC_DMA, DMAREQ_SPI0_TX, &Chip_DMA_Table[DMAREQ_SPI0_TX]); // Setup data transfer --> Start Sending data? Chip_DMA_SetupChannelTransfer(LPC_DMA, DMAREQ_SPI0_TX, Chip_DMA_Table[DMAREQ_SPI0_TX].xfercfg); #else // Setup SPI Transfer setup tx0Setup.Length = SPI_BUFFER_SIZE; tx0Setup.pTx = txBuf; tx0Setup.pRx = rxBuf; tx0Setup.RxCnt = tx0Setup.TxCnt = 0; tx0Setup.DataSize = 8; #if(INTERRUPT) // Send SPI via interrupt mode NVIC_EnableIRQ(SPI0_IRQn); Chip_SPI_Int_RWFrames(LPC_SPI0, &tx0Setup); Chip_SPI_Int_Cmd(LPC_SPI0, SPI_INTENSET_TXDYEN | SPI_INTENSET_RXDYEN | SPI_INTENSET_RXOVEN | SPI_INTENSET_TXUREN, ENABLE); #else // Send SPI via blocking mode Chip_SPI_WriteFrames_Blocking(LPC_SPI0, &tx0Setup); #endif #endif // Enter an infinite loop while(1) { __WFI(); } return 0 ; } |