lpcware

Glitch Filter Clock Divide Register Selection problem

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by mvinger on Sun Jul 21 11:02:24 MST 2013
I am using an LPC812 and LPCXpresso.
I have just attempted to use the Glitch Filters on the inputs and found something fairly odd.
To use IOCONCLKDIV0 I must set the PIO0_x register CLK_DIV to use IOCONCLKDIV6 or I must write the value I wish to use in IOCONCLKDIV6. It seems there is a reversal of the selection/use.

MTV2

Outcomes