TxTest=0xA0A0A0A0; RxTest=0; RxTest1=0; dmaDesc.source = DMA_ADDR((&TxTest)); //dmaDesc.dest = DMA_ADDR((&(LPC_SPIMASTERPORT->TXDATCTL))); dmaDesc.dest = DMA_ADDR((&RxTest)); dmaDesc.next = DMA_ADDR(&(dmaDesc1)); dmaDesc1.xfercfg =(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_WIDTH_32 |DMA_XFERCFG_SETINTA | DMA_XFERCFG_CLRTRIG ); //dmaDesc1.source = DMA_ADDR(&(LPC_SPIMASTERPORT->RXDAT)); dmaDesc1.source = DMA_ADDR((&TxTest)); dmaDesc1.dest = DMA_ADDR(&RxTest1); dmaDesc1.next= DMA_ADDR(0); NVIC_EnableIRQ(DMA_IRQn); /* Setup transfer descriptor and validate it */ Chip_DMA_SetupTranChannel(LPC_DMA, DMA_CH0, &dmaDesc); Chip_DMA_SetValidChannel(LPC_DMA, DMA_CH0); Chip_DMA_SetupChannelTransfer(LPC_DMA, DMA_CH0,(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_WIDTH_32 )); // /* Setup data transfer and software trigger in same call */ |
typedef struct { uint32_t xfercfg;/*!< Transfer configuration (only used in linked lists and ping-pong configs) */ uint32_t source;/*!< DMA transfer source end address */ uint32_t dest;/*!< DMA transfer desintation end address */ uint32_t next;/*!< Link to next DMA descriptor, must be 16 byte aligned */ } DMA_CHDESC_T; |