LPC5411x - JTAG boundary scan and SWD / Flexcomm pin descriptions

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by bhaack on Tue Apr 05 05:14:57 MST 2016
since there is no dedicated forum for the LPC5411x yet, I will post my questions here:

in contrast to previous devices according to datasheet v1.3 LPC5411x uses four separate pins for SWDIO/TMS and SWCLK/TCK. Can I re-connect them to use only one single 10pin-header for SWD-debugging and JTAG boundary scan, or are there technical reasons for spreading these functions to separate pins?

Is /TRST an optional pin for boundary scan, since it it missing on the 10-pin cortex debug connector? Segger uses Pin 9 for /TRST, which is labeled as GNDDetect. Will connecting /TRST to pin 9 interfere with LPCLink2/SWD?

PIO0_23 and PIO0_25 have ambiguous descriptions in table 4 - I assume RTS is in both cases correct for FC1 and FC4?