How can i enable m0+ core on NXP LPC54102 microcontroller?

[lpcware]

Content originally posted in LPCWare by waleed on Thu Mar 26 12:49:29 MST 2015
Hi,

I want to run a bare metal application on m0+ core of NXP LPC54102, but i don't know how can i wake up the core from sleep? What registers should i look into to wake up the m0+ core? Since m0+ core can only be enabled by m4 core so, how can i use m4 core to wake up m0+ core?

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Apr 16 05:46:00 MST 2015
Thanks for the script file, it's the standard one which just includes the information about the debug access port number for CM4 and CM0+.
So we can exclude the script from the discussion.

To have a clean starting point for this investigation the core(s) should do nothing at all when they come out of the bootloader. This means that the reset Handler should just have as first instruction a jump on itself. Every successful debugger access will then end up there.
(The KEIL example I used physically stopped the M0+ clock and put it reset in the startup file. Therefore the debugger didn't get access. This is different than putting it into sleep with WFI).

OK, let's come to the physical implementation. As already said, the LPC54102 can be configured during production by writing values into a hidden flash sector. When the MCU starts up, both CPUs start up as well and both copy over the value in the flash sector. At this point the LPC54102 gets its configuration with regards to the cores: single core (M4 or M0+) or dual core (with either M4 or M0+ being the master).

The LPC54102 is a dual core chip configuration, so let's concentrate on this scenario.

Both CPUs query the index sector value to see who should be the master. Each CPU also queries their own CPU ID to find out if they are the M4 or M0+. The CPU that discovers that it is the master continues to boot. Meanwhile the CPU that discovers that they are to be the slave goes into a loop of WFI (with no interrupts enabled).

m0_sleep
        WFI; if M4 is master we go to sleep
b        m0_sleep

In this way you save all the power but the slave CPU is still accessible by the debugger and in fact the debugger can actually force it to go to a different address if the user chooses to do so. A very positive point here also is the fact, that when a reset occurs, you never lose contact with the slave or master CPU from the debugger.

So what you see in your environment is correct and expected.


Regards,
NXP Support Team.

[lpcware]

Content originally posted in LPCWare by waleed on Wed Apr 15 00:32:25 MST 2015
Hi NXP Technical Support

I have attached the script file to connect to m0+ core.

I am not using LPCXpresso so i cannot tell information about debugger box.

I tested it with Keil and a CMSIS-DAP debugger box and it works as I expect it:
- access to the Cortex-M4 works (AP = 0)
- access to the Cortex-M0+ is rejected (AP = 1) as this core is inactive

Is it possible that access to Cortex-M0+ is rejected because your application might be putting M0+ core to sleep? I am saying this because i have been through startup files and they put m0+ core to sleep.

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Apr 14 07:34:03 MST 2015
For sure it's some force of technology  8-)

Can you please send me the Segger script you use and tell me which debugger box you use.

I tested it with Keil and a CMSIS-DAP debugger box and it works as I expect it:
- access to the Cortex-M4 works (AP = 0)
- access to the Cortex-M0+ is rejected (AP = 1) as this core is inactive

Regards,
NXP Support Team

[lpcware]

Content originally posted in LPCWare by waleed on Mon Apr 13 09:40:07 MST 2015
As the configuration of the flash index sector is done during chip production, the LPC54102 is delivered with a fixed configuration --> with Cortex-M4 as master. The other option (M0+ is master) is just an option at the moment. This means that the Cortex-M0+ is indeed in sleep mode after power-up/reset and needs to be woken up by the M4

I have a script file from Segger to connect to m0+ core on LPC54102 board.That script file can be used to connect to m0+ core, only after m0+ has been enabled. The problem is that if i use that script file alone (that is without enabling m0+ core ), i am able to connect to m0+ core and i am able to debug my application on that core.Thus i can have stand alone debugging session on m0+ core, using only a single script file.

Now it seems to me that either there is something runing on m4 that enables m0+ or script file enables m0+ core.

So as far as " something runing on m4 that enables m0+" is concerned, i can assure you that this is not the case.I can also say this because even after power cycle of LPC54102 board, i am able to connect to m0+ core just by using that single script file and debug my application on that core.

As far as script file provided by SEGGER is concerned, i can also say that it is not enabling the core.Now to be sure i also asked SEGGER literally like three times and they told me that "Script file is *definetely not* enabling the core".

So my question is that what is hapening here? If m0+ goes to sleep after power up then how am i able to debug my application on that core using a single script file (which does not wake up m0+ from sleep)? Is some force of nature waking up m0+ core  :bigsmile: ?

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Apr 13 08:52:49 MST 2015
Puh, let's try to get this issue sorted out  8-)

[list]
  [*]  Just for the books: The dual core structure in LPC54102 is different compared to the LPC4300.
  [*]  In the LPC54102 both cores start to execute the ROM bootcode. This ROM code is compiled for M0+, so both cores can execute the instructions.
  [*]  One of the first instructions reads a bit from the hidden flash index sector and stores it into the currently undocumented register at 0x4000 0300. This flash sector also contains calibration data for the flash, the IRC etc. It is locked after reading from it.
  [*]  Depending on this bit, one of the cores is put into sleep mode with a WFI command --> clock to the core gets stopped. The other core continues to execute the ROM bootcode.
  [*]  Coming out of the bootcode the user code can check which of the cores is active by reading the register at 0x4000 0300 and maybe also asking for the cpu id. Whatever comes next, it's already application specific.
  [*]  As the configuration of the flash index sector is done during chip production, the LPC54102 is delivered with a fixed configuration --> with Cortex-M4 as master. The other option  (M0+ is master) is just an option at the moment. This means that the Cortex-M0+ is indeed in sleep mode after power-up/reset  and needs to be woken up by the M4. How to do this is shown in the multicore example of LPCOpen (file cpuctrl_540xx.c)
[/list]

Hope this clarifies the situation,
NXP Support Team

[lpcware]

Content originally posted in LPCWare by waleed on Sun Apr 12 04:35:08 MST 2015
Hi NXP Technical Support,

I want to confirm that m0+ core does not go to sleep after power up, right? I know what's the answer but i just want to confirm from you,so kindly do answer this question.

And thanks for all the help  :)

[lpcware]

Content originally posted in LPCWare by waleed on Fri Apr 10 15:22:20 MST 2015
Hi NXP Technical Support,

So what you are saying is that after power up both cores are active and no core is in sleep mode?(kindly do answer this question as it would remove a lot of confusion in my mind)

If that's the case then, in my humble opinion, this should be really documented in UM10850 because in UM10850:

1. There is no information about which core is the master and which core is slave core.
2. CH#5 (in UM10850) also dosen't list properly that what happens after power up.
3. There is no information about CPU Control register, Coprocessor boot register and coprocessor stack register. All of these registers are extremely important.
4.There is no information about using both cores on LPC 5410x board, that is how we can use both cores at the same time and what measures should be taken to avoid any problems during multicore usage. Yes AN11609 explains multicore usage but that is about how the application in LPCOpen package is working or how Keil application is using both cores. what i am talking about is that there should be more generic explanation of the multicore usage in UM10850.
5. There is no proper information about different low power modes, how we can get into these modes and how we can wake the core from those modes.Yes AN11611 explains different low power modes but this should also be documented in UM10850.


Also the application notes should mention that which information is specific only to this application and which information is actual part of NXP LPC5410x board. I am saying this because when i read section 5.2 in AN11609, i believed that "after power up m4 is master core and m0+ is slave core and m4 remains active and m0+ core goes to sleep and it is the job of application runing on m4 to wake up m0+ core".
Now this is not just my understanding, everyone i know who has NXP LPC5410x board thinks that "after power up m4 is master core and m0+ is slave core and m4 remains active and m0+ core goes to sleep and it is the job of application runing on m4 to wake up m0+ core".
The point i am trying to explain is that reading the section 5.2 in AN11609 will make people believe that after power up m0+ goes to sleep which is totally not the case.

After your last comment which says " What happens afterwards (whether the Cortex-M0+ core goes to sleep, or any other behavior that you are seeing), is entirely application dependent", I am also just a little bit disappointed that i have spent a lot of time enabling m0+ core but the reality is that it does not goes to sleep after power up.All that is written in application notes AN11609 and AN11611 is application dependent.

Thanks for all the help and your help is always much needed and appreciated  :)

[lpcware]

Content originally posted in LPCWare by nerd herd on Fri Apr 10 07:42:00 MST 2015
Hi waleed,

The reset values in the UM are correct; both cores are initially turned on and execute code at address 0x0. What happens afterwards (whether the Cortex-M0+ core goes to sleep, or any other behavior that you are seeing), is entirely application dependent. To help clear this up, I will walk you through the the LPCOpen Keil projects. If you download the latest LPCOpen for the LPC5410x, unzip the archive and open the keil_startup_lpc5410x.s file located here: \applications\lpc5410x\startup\

Starting on line 154 is the Reset_Handler which is the the application code that is initially run by both cores. If you read the assembly (or the much more readable comments), you will see that both cores will read the CPUCTRL register to find out who is master (and as I said in a previous post, it will always be the Cortex-M4 after a reset). After this, they will jump to different assembly "boot code". The Cortex-M0+ core will find that there is no slave boot address for him and will just go to sleep. If you are running the the multicore blinky example, the Cortex-M4 core will set up the necessary things for the slave core (slave boot address, stack pointer), and then bring the slave core out of sleep mode as it now has code to execute.

[lpcware]

Content originally posted in LPCWare by waleed on Thu Apr 09 23:20:25 MST 2015
My first question is that (this question might sound really stupid but please bear with me and kindly do answer it), After power up m4 is the master core and m0+ is slave core, also m4 remains active and m0+ goes to sleep and this would happen after every power up since it's the boot process, right?

Yes this is correct. The master core is indicated by a bit in the CPUCTRL register, and the default value upon reset will always make the Cortex-M4 core the master.

I asked the above question because if after power up m0+ goes to sleep (which means that it's clock would be disabled) then why the reset value of "CM0CLKEN" bit in CPU Control register is "1" (AN11608 pg 7).

Which leads me to my another question that, does m0+ goes to sleep after power up?

You help is much needed and appreciated  :)

[lpcware]

Content originally posted in LPCWare by nerd herd on Thu Apr 09 13:48:00 MST 2015
Hi waleed,

My first question is that (this question might sound really stupid but please bear with me and kindly do answer it), After power up m4 is the master core and m0+ is slave core, also m4 remains active and m0+ goes to sleep and this would happen after every power up since it's the boot process, right?

Yes this is correct. The master core is indicated by a bit in the CPUCTRL register, and the default value upon reset will always make the Cortex-M4 core the master.

From "the system clock to the ARM Cortex-M4 and Cortex-M0+ core is stopped" this is what i understand, that clock to a core (core could be m4 or m0+) is disabled which means that if clock to a core is enabled then it should enable/wakeup the core from sleep mode. Clock to a core can be enabled by writing to CPU Control Register which lies at address "0x40000300".

Another way to enable m0+ core from sleep is following (i don't know why we need to reset m0+ core to wake it up from sleep as logically enabling the clock to core should do it):
Write "0xC0C4006D" to CPU Control register it would reset m0+ core and would disable it's clock so after writing "0xC0C4006D" i need to write "0xC0C4004D" to CPU Control register to enable the clock for m0+ core. This would take m0+ core out of reset/sleep.

The typical (and recommended) way to wake-up the other core from Sleep mode is to generate an interrupt, such asa mailbox interrupt. Is there a reason why you would want to try to wake up a core through a means other than an interrupt? And yes, do not reset the core just to wake it up. A reset does not allow the core that is being reset to resume where it was left off (which makes the behavior a reset, not a sleep/wakeup event).

My last question is that, is there a plan to release an update version of UM10850?

Yes there should be an updated version of the UM that will be released very soon! Keep your eyes peeled ;)

[lpcware]

Content originally posted in LPCWare by waleed on Thu Apr 09 12:51:11 MST 2015
Hi NXP Technical Support


AN11609 page #12 (section 5.2) says that:

"After a power up or hardware reset, the boot process is handled by the on-chip boot ROM and is always executed by the Cortex-M4F core. After the bootloader code and the system init section, the Cortex-M4F can set up the environment for the Cortex-M0+.

• Provide a reset handler start address to the Cortex-M0+
• Provide a stack pointer address to the Cortex-M0+

After that the Cortex-M0+ can be taken out of reset by the Cortex-M4F."


My first question is that (this question might sound really stupid but please bear with me and kindly do answer it), After power up m4 is the master core and m0+ is slave core, also m4 remains active and m0+ goes to sleep and this would happen after every power up since it's the boot process, right?


Application note AN11611 says that "In Sleep mode, the system clock to the ARM Cortex-M4 and Cortex-M0+ core is stopped and execution of instructions is suspended until either a reset or an interrupt occurs."


From "the system clock to the ARM Cortex-M4 and Cortex-M0+ core is stopped" this is what i understand, that clock to a core (core could be m4 or m0+) is disabled which means that if clock to a core is enabled then it should enable/wakeup the core from sleep mode. Clock to a core can be enabled by writing to CPU Control Register which lies at address "0x40000300".

Another way to enable m0+ core from sleep is following (i don't know why we need to reset m0+ core to wake it up from sleep as logically enabling the clock to core should do it):
Write "0xC0C4006D" to CPU Control register it would reset m0+ core and would disable it's clock so after writing "0xC0C4006D" i need to write "0xC0C4004D" to CPU Control register to enable the clock for m0+ core. This would take m0+ core out of reset/sleep.

My second question is that, how much am i correct in above two paragraphs?


My last question is that, is there a plan to release an update version of UM10850?

For now that's all and your help is always much needed and appreciated. :)

[lpcware]

Content originally posted in LPCWare by nerd herd on Thu Apr 09 10:23:20 MST 2015
Hi waleed,

Can you tell me in detail what you have been able to accomplish and what is your goal? From there, we can break down your goal into incremental steps and go through them one by one.

[lpcware]

Content originally posted in LPCWare by waleed on Tue Apr 07 09:40:31 MST 2015
Hi NXP Technical Support,

Thanks for all the help before, but still i really need your help.

[lpcware]

Content originally posted in LPCWare by waleed on Mon Apr 06 02:15:57 MST 2015
Hi NXP Techinal Support,

Can you kindly provide me the bit descriptions of the following registers CPU Control Register, Coprocessor Boot Register and Coprocessor Stack Register?

[lpcware]

Content originally posted in LPCWare by waleed on Thu Apr 02 08:26:26 MST 2015
Hi NXP Technical Support,

Can i enable m0+ core using DMA interrupt?

The steps i am using to enable the core are as follows:

1.set the DMA clock in AHBCLKCTRL0 register.

2.Set the DMA interrupt in NVIC( by using ISER0 register)

3. Set the DMA interrupt in Start enable register 0 (STARTERP0)

4.Generate the interrupt using interrupt set pending register, by writing the mask that changes the DMA interrupt state to pending (ISPR0).


Can you kindly confirm that am i using the right steps? Am i on the right path?

Thanks for the help.

[lpcware]

Content originally posted in LPCWare by waleed on Thu Apr 02 08:25:08 MST 2015
My code is not enabling m0+ core as i am not able to debug it.

[lpcware]

Content originally posted in LPCWare by nerd herd on Thu Apr 02 07:19:03 MST 2015
Hi waleed,

The LPCOpen examples should work no problem on the LPCXpresso board. Did you successfully program the MCU code for both cores? If so, you should be able to see the LED constantly blink. That indicates both cores are successfully communicating via mailbox. To confirm that the Cortex-M0+ core is working, you modify the project such that the Cortex-M4 core goes to sleep and the Cortex-M0+ constantly blinks the LED by itself, using something like the systick interrupt like the single core blinky example.

[lpcware]

Content originally posted in LPCWare by waleed on Thu Apr 02 04:07:38 MST 2015
I am using LPCXpresso evaluation board.

[lpcware]

Content originally posted in LPCWare by starblue on Thu Apr 02 03:05:33 MST 2015
No, I mean AN11608.

As far as I can tell the information in AN11609 is also in the currently available user manual (which doesn't mean you shouldn't read it anyway), while AN11608 page 7 documents a register CPUCTRL that is not yet in the user manual.

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Thu Apr 02 02:03:10 MST 2015
I think you mean AN11609?
http://www.nxp.com/documents/application_note/AN11609.zip