M0+ not working when M4 goes in deep sleep mode

[lpcware]

Content originally posted in LPCWare by filartrix on Fri Jul 10 06:46:59 MST 2015
Hi all,
my purpose is to have the M0 running, while the M4 is in "POWER_DEEP_SLEEP" or "POWER_POWER_DOWN".
I started from multicore blinky project and made the following modifications:
- removed any reference to mailboxes
- set the clock source to IRC clock and turned of PLL
- added systick ISR and configuration to M0 code to led a led blink (the LED is thus driven by the M0+)

here's an extract of the M4 code:

int main(void)
{
uint32_t *jumpAddr, *stackAddr;

SystemCoreClockUpdate();
Board_Init();
setupClocking(); // Turn off PLL sent IRC as clock source
SystemCoreClockUpdate(); //MCU now runs @12MHz

        stackAddr = (uint32_t *) (*(uint32_t *) M0_BOOT_STACKADDR);
jumpAddr = (uint32_t *) (*(uint32_t *) M0_BOOT_ENTRYADDR);
Chip_CPU_CM0Boot(jumpAddr, stackAddr);  //Boot the M0

    POWER_MODE_T powerMode  = POWER_DEEP_SLEEP;
    /* Set voltage as low as possible */
    Chip_POWER_SetVoltage(POWER_BALANCED_MODE, Chip_Clock_GetMainClockRate());
    /* Now enter sleep / power down state */
    Chip_POWER_EnterPowerMode(powerMode, (SYSCON_PDRUNCFG_PD_WDT_OSC | SYSCON_PDRUNCFG_PD_SRAM0A
    | SYSCON_PDRUNCFG_PD_SRAM0B | SYSCON_PDRUNCFG_PD_SRAM1));

while (1) {
}

The M0 firmware simply le a led blink.
the blink is stopped when the M4 goes in low power mode

I read someone asking whether is possible to let the M0 behave as master, could this be a solution?
or am I missing something?

[lpcware]

Content originally posted in LPCWare by nerd herd on Fri Jul 10 17:08:52 MST 2015

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Quote: filartrix
I read someone asking whether is possible to let the M0 behave as master, could this be a solution?
or am I missing something?

---

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Quote: embd02161991
Hi,

The Deep-sleep and power-down modes affect the entire system. In both modes, the clock to all CPUs is shut down and the peripherals receive no internal clocks. So both M0+ and M4 will not have clock in Deep sleep and power down modes.

Thanks
NXP Technical Support

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For clarity, I would like to add onto this answer by saying that making the M0+ core a master will not change anything.

[lpcware]

Content originally posted in LPCWare by embd02161991 on Fri Jul 10 14:39:44 MST 2015
Hi,

The Deep-sleep and power-down modes affect the entire system. In both modes, the clock to all CPUs is shut down and the peripherals receive no internal clocks. So both M0+ and M4 will not have clock in Deep sleep and power down modes.

Thanks
NXP Technical Support