Can i wake up alone M0 core?

[lpcware]

Content originally posted in LPCWare by zhongjru on Wed Jan 14 02:20:20 MST 2015
When the system enters a low-power mode, can i wake up alone M0 core interrupt it?

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Fri Apr 03 12:07:20 MST 2015
Read these application notes
http://www.nxp.com/documents/application_note/AN11609.zip
http://www.nxp.com/documents/application_note/AN11608.zip

These provide the information you are requesting

[lpcware]

Content originally posted in LPCWare by waleed on Fri Apr 03 11:09:18 MST 2015
Hi Zhongjru,

Can you kindly provide me with any suggestions on how i can enable m0+ core on NXP LPC5410x board.

[lpcware]

Content originally posted in LPCWare by waleed on Sun Mar 29 12:41:05 MST 2015
Hi Zhongjru,

I want to run bare metal application on m0+ core of NXP LPC54102. After Power On Reset both cores boot but m0+ is put to sleep. Thus if i want to run my application on m0+ core i would have to enable it first.

Can you kindly guide me about how can i write an initialization code that would enable the m0+ core on LPC54102?

Thanks...

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Tue Jan 20 23:41:26 MST 2015
The wake up concept is about waking up the core. So yes, these peripherals when configured can wake up the core.

[lpcware]

Content originally posted in LPCWare by zhongjru on Sun Jan 18 20:35:16 MST 2015
How to understand about Start enable registers?
"The STARTERP0 and STARTERP1 registers enable an interrupt for wake-up from deep-sleep and power-down modes.Some interrupts are typically used in sleep mode only and will not occur during deep-sleep or power-down modes because relevant clocks are stopped. However, it is possible to enable those clocks (significantly increasing power consumption in the reduced power mode), making these wake-ups possible."
If peripheral interrupts will be config to enable during deep-sleep or power-down modes,and enable Start enable registers,can i think core will be wake up during deep-sleep or power-down modes?

[lpcware]

Content originally posted in LPCWare by nerd herd on Fri Jan 16 09:08:00 MST 2015
Hi Zhongjru,

Correct. If the Cortex-M0+ core is in active mode, then the Cortex-M4F core can only be in Sleep mode because the other three low power modes would shutdown both cores. The same is true if the roles of the two cores were swapped (Cortex-M4F in active mode).

[lpcware]

Content originally posted in LPCWare by zhongjru on Thu Jan 15 20:39:37 MST 2015
Thank you for your help.
"Nested Vectored Interrupt Controller that is an integral part of each CPU."this sentence is the key.
Now,i can wake-up M0 core alone.
"In terms of low power modes, Sleep mode can be used on one core and not the other. The other three low power modes, Deep-sleep, Power-down, and Deep Power-down, will force both cores into the low power mode since they shut down the chip."so,M4 must in sleep mode when M0 is active,other three low power mode can't run in M4.Is corrent？

[lpcware]

Content originally posted in LPCWare by mc on Thu Jan 15 09:18:59 MST 2015
Hi zhongjru,
For better understanding about interrupt on LPC54100, I recommend you to read chapter (Chapter 3: LPC5410x Nested Vectored Interrupt Controller
(NVIC) at page 12/437 of UM10850. See link below

http://www.nxp.com/documents/user_manual/UM10850.pdf

[lpcware]

Content originally posted in LPCWare by starblue on Thu Jan 15 02:45:03 MST 2015
No, the NVIC is part of the core so each core has its own NVIC.

[lpcware]

Content originally posted in LPCWare by zhongjru on Thu Jan 15 02:30:08 MST 2015
Thank you for your reply.
Since M0 and M4 share the same NVIC, thus triggering an interrupt can not only just wake-up M0. But I found that you can use the NMI's NMISRC register individually trigger M0 core, I think this is the only way.

[lpcware]

Content originally posted in LPCWare by nerd herd on Wed Jan 14 08:53:09 MST 2015
Hi zhongjru,

If you enable a specified wake-up source ISR on only one core, then only that core will wake-up when that ISR is triggered.

Keep in mind that the terminology we use (Sleep mode, Deep-sleep, etc.) are states the MCU is in based on what is on and off. The main thing I would advise you to understand is that Sleep mode is defined to be when the system clock for that specified core is off, but other clocks can still be on (i.e. peripheral clock, main clock for the other core, etc.). The other three low power modes are defined to be when the entire main clock is off (among other things).

So let's say you enter Power-down mode and only wake-up the Cortex-M0+ core. The Cortex-M4F core is technically still in a low power mode, but because the Cortex-M0+ core is on and operating, the MCU is no longer in Power-down mode. The current state of the cores would be drawing power closer to when the Cortex-M4F core is in Sleep mode and the Cortex-M0+ core is in active mode.

Let me know if there is confusion on this topic.