lpcware

LPC2103 PLL setup with Keil µVision and Peripheral Clock, what is XCLKDIV?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by Han_Mono on Mon Mar 07 05:54:03 MST 2016
Hello everyone,


I'm currently working on revising an old project which was handed over to me with a LPC2103 where I need to port all communication from IIC to Uart.
Sounds easy and it should be, but I'm running into clock problems.

Setup:

Xtal: 16,9344MHz
PLL multiplier: 3
APDIV: 4 (called VPBDIV in microvision)

Therefore the CPU should clock at 50,7MHz, the Peripheral/uart clock should run at 12,7MHz and I decided to run Uart at 38400 Baud.

But in the startup.s/Keil's config wizard there's a something called XCLKDIV, which I assume is the external oscilator input divider which was also set to 4.
No my real problem is that I do not understand or find what XCLKDIV really is and what it does, because to me it seems it doesnt act as a divider but as a multiplier.

Example: I have Uart0 configured to run at 38400 Baud but it actually runs at 156K, so 4 times the Baud I set. Setting XCLKDIV to 1 (== CLK) it runs at 38400 Baud but some other peripherals stop working correctly.

Could someone please tell me what that XCKDIV is?

best
Han

Outcomes