LP2387 ENET_REF_CLK specs

[lpcware]

Content originally posted in LPCWare by eeckenrode on Thu Feb 25 09:04:56 MST 2016
Hello,
We have a two board design where we connect a LAN8720A daughter board to a third party LPC2387 main board that we purchase.  We have noticed some radiated emission issues to the point we cannot pass emission certifications for our product.  The ENET_REF_CLK passes through a connect between the boards.  This is the source of our emissions issue.  We have been able to reduce emissions significantly by slowing the edges on the ENET_REF_CLK with a capacitor.  We are looking for LPC2387 timing requirements for the MAC interface (in particular the ENET_REF_CLK) because we need to determine if we are violating any timing requirements.  We are most curious if rounding the ENET_REF_CLK signal is a major concern?

-notes-
Placed a 47pF cap on ENET_REF_CLK.  This essentially makes the clock signal mostly sinusoidal. 
Trace lengths on Daughter Card - 0.25 inches (impedance matched)
Trace lengths on Main Board - 0.375 inches
Connector between boards
As tested with additional capacitor, signal integrity seems good and data transmission seems OK in the lab.



Thanks,
Eric

[lpcware]

Content originally posted in LPCWare by DF9DQ on Wed Mar 02 00:24:03 MST 2016
Hi Eric,

A big issue will probably be the drift of the actual 0->1/1->0 thresholds of the clock input due to component variations and in particular temperature. Small changes of the threshold result in large timing uncertainties if the clock slopes are slow.

I've seen cases where adding much smaller caps (up to 10p) was beneficial, but then the intended delay due to the slowed down slope was only moderate.

My worries are that your positive lab results may not be reliably repeatable in production.

Rolf