Do LPC2478’s timers support INTERRUPT, STOP and RESET on match?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by dyerfdf on Wed Jan 06 12:16:34 MST 2016
I am enabling TIMER1 to INTERRUPT, STOP and RESET on a match (i.e. set MR0I, MR0R and MR0S in T1MCR). My timer handler then changes the match register value and re-enables the timer, but I have to manually clear the TC register for proper operation. Why do I need to clear the TC if it is set to reset automatically (via MR0R)?

One line of code does not sound significant, but my application is displaying images from an SD Card to an SVGA display, so the less time the CPU accesses the APB bus, the better. Yes, I have the AHB arbitration tweaked as well. Every access to the TIMER registers has to arbitrate for the bus in between the LCD and DMA from the SD Card.

I found a thread in an NXP forum that *suggested* that ‘INTERRUPT & STOP’ or ‘INTERRUPT & RESET’ were possible, but all three were not. If that is true, that would explain what I am seeing, but the User Manual (UM10237, rev 4) does not state this. Code excerpts below:

// Setup Timer1 to INTERRUPT, STOP and RESET on MR0
T1TCR=0; // disable counting
T1TCR=1; // reset counter
T1TCR=0; // release reset
T1CTCR=0; // set to Timer Mode; every rising PCLK edge
T1MCR=7; // set MR0I to INTERRUPT on MR0, set MR0R to RESET on MR0, set MR0S to STOP TC and PC on MR0
T1PR=0; // so not use prescaling
T1MR0=5000; // set initial match register value (MR0)
T1IR=0xF; // clear any pending interrupts
VICIntSelect=(1<<5); // set Timer1 as FIQ
VICIntEnClr=(1<<5); // Disable Interrupt
VICIntEnable=(1<<5); // Enable Interrupt

Then in my timer handler, I am trying to change the interval time and then re-enable the counter

__ramfunc void timer1Handler (void)  /* FIQ handler*/
< omitted some short non-timer related code >

T1TC=0; // clear the counter register even though MR0R is set  - WHY IS THIS NEEDED??
T1MR0=1000; // set a new match value
T1TCR=1; // enable counter
T1IR=1; // clear interrupt flag for MR0

Unless I specifically use the statement "T1TC=0", the timer counter doesn't reset to zero and instead the new match is missed and I don't get an interrupt until the timer rolls over.

Could running the handler as a RAM function be causing an issue? Should I clear interrupt flag on entry as opposed to exit?

Application info:
CPU clock is 72Mhz; timer PCLK is 18Mhz.

LPC2478 User Manual (UM10237, rev 4)
6.7 The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register.

6.8 The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter.
MR0I=1 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
MR0R=1 - Reset on MR0: the TC will be reset if MR0 matches it.
MR1I=1 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.