LPC2468 Hardware Interface question

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by mountainbarn on Thu May 28 13:18:35 MST 2015

I am currently trying to solve a HW interface problem for a client.
The circuit in question has 4 Dual UART devices (SC16C2550B) mapped
into external memory space (CS1) connected to a LPC2468FBD208 (Rev D). The circuit
use the lowest 3 address lines A0-A2 to select 1 of the 8 registers in the UART.
The memory space is configured to be 8 bit as can be seen in the screen shot
of the registers dump from IAR IDE. The next 3 Address lines drive a
3 to 8 decoder enabled by CS1 to select 1 of the 8 UARTS.
The problem is that even though the test code (see attachment) is executing a single
LDRB instruction, 2 consecutive reads with the address incrementing, occur at the HW level.
This is obviously a problem when reading a UART register as this will affect operation.

The oscilloscope trace shows the read cycle with CS, A0, A1, and Read signals.

Does anyone have any Idea/Suggestions? Am I understanding the I/F requirements correctly?