LPC11U68 wrong GPIO Address range

[lpcware]

Content originally posted in LPCWare by Fox_Mulder on Fri Aug 08 10:00:50 MST 2014
Hi,

i'm new to the LPC11U68 and i'm encountering a little problem. In the PDF Manual v1.3 (UM10732) on page 102 the offset for the addresses is different from what the Keil debugger and lpc11u6x.h header file shows me.

In the Manual the offset for W0..W31 is 0x1000 to 0x105C (96 Addresses = 24 Regs x 4 Bytes).
The first problem is the wrong W31 which should be W23 because W24 to W31 are not present at this controller.

But the main problem is the offset of 0x1000 which i think is not right. The header file defines the following offsets:
uint8_t   B[88];           /*Byte pin registers*/
uint32_t  RESERVED0[42];
uint32_t  W[88];         /*Word pin registers*/
uint32_t  RESERVED1[1896];
uint32_t  DIR[3];         /*Port Direction registers*/

This leads for me to 88 + 42*4 = 256 / 0x100 as offset for the Wxx Registers which is the same the Keil Debugger shows. So am i right that the offset shouldn't be 0x1000 but 0x100 for the W Registers?

Ciao,
        Rainer

[lpcware]

Content originally posted in LPCWare by Fox_Mulder on Sun Aug 17 05:28:55 MST 2014
Thanks for the fast support. I downloaded the latest LPC11U6x.svd file (v0.8) and the gpio address offset for W is fixed from 0x100 to 0x1000. When i generate the LPC11U6x.h header file with svdconv.exe i see four differences compared to the modified keil header file. I think at least the missing ADC_B_IRQn entry is important. The naming convention for the USART(0) is more cosmetically and i don't find the missing AHBMATRIXPRIO in the manual. I don't know what the purpose of PendSV_IRQn is for.

Here is the diff for the header file:

--- /Keil-MDK/ARM/Pack/ARM/CMSIS/4.1.1/CMSIS/Utilities/LPC11U6x.hSun Aug 17 14:06:20 2014
+++ /Keil-MDK/ARM/Pack/Keil/LPC1100_DFP/1.1.0/Device/Include/LPC11Uxx/LPC11U6x.hSun Aug 17 14:02:51 2014
@@ -39,6 +39,7 @@
   HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
   SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
   DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
   SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
 /* ---------------------  LPC11U6x Specific Interrupt Numbers  -------------------- */
   PIN_INT0_IRQn                 =   0,              /*!<   0  PIN_INT0                                                         */
@@ -62,7 +63,7 @@
   CT32B0_IRQn                   =  18,              /*!<  18  CT32B0                                                           */
   CT32B1_IRQn                   =  19,              /*!<  19  CT32B1                                                           */
   SSP0_IRQn                     =  20,              /*!<  20  SSP0                                                             */
-  USART_IRQn                    =  21,              /*!<  21  USART                                                            */
+  USART0_IRQn                   =  21,              /*!<  21  USART0                                                           */
   USB_IRQn                      =  22,              /*!<  22  USB                                                              */
   USB_FIQ_IRQn                  =  23,              /*!<  23  USB_FIQ                                                          */
   ADC_A_IRQn                    =  24,              /*!<  24  ADC_A                                                            */
@@ -70,6 +71,7 @@
   BOD_WDT_IRQn                  =  26,              /*!<  26  BOD_WDT                                                          */
   FLASH_IRQn                    =  27,              /*!<  27  FLASH                                                            */
   DMA_IRQn                      =  28,              /*!<  28  DMA                                                              */
+  ADC_B_IRQn                    =  29,              /*!<  29  ADC_B                                                            */
   USBWAKEUP_IRQn                =  30               /*!<  30  USBWAKEUP                                                        */
 } IRQn_Type;
 
@@ -714,7 +716,8 @@
                                                          filter                                                                */
   __IO uint32_t  BODCTRL;                           /*!< Brown-Out Detect                                                      */
   __IO uint32_t  SYSTCKCAL;                         /*!< System tick counter calibration                                       */
-  __I  uint32_t  RESERVED11[6];
+  __IO uint32_t  AHBMATRIXPRIO;                     /*!< AHB matrix priority configuration                                     */
+  __I  uint32_t  RESERVED11[5];
   __IO uint32_t  IRQLATENCY;                        /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
   __IO uint32_t  NMISRC;                            /*!< NMI Source Control                                                    */
   __IO uint32_t  PINTSEL0;                          /*!< GPIO Pin Interrupt Select register 0                                  */

Ciao,
        Rainer

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Tue Aug 12 00:39:00 MST 2014
0x1000 is correct.

Attached you can find an update file for LPCXpresso 7.3.0 which should correct the display of these registers in the Peripheral View (for LPC11U6x and LPC11E6x parts).

To install, ensure that LPCXpresso is not running, then extract the files from the ZIP there into:

[lpcxpresso_install_dir]\lpcxpresso\bin

This fix will be included in the next LPCXpresso release.

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by Fox_Mulder on Sat Aug 09 03:32:18 MST 2014
I'm still experimenting with the IDE of choice for me and now i installed LPCXpresso and imported the LPCopen Projects for the LPC11U68. Now when i take a look in the file inc/gpio_11u6x.h in the project lpc_chip_11_u68x the comment states that the W registers are located at 0x1000. The LPCopen include also seems to represent the reserved area a bit different compared to the Keil version.

[u]Keil-MDK LPC11U6x.h include:[/u]
typedef struct {/*!< GPIO_PORT Structure*/
  __IO uint8_t B[88];/*!< Byte pin registers*/
  __I  uint32_t RESERVED0[42];
  __IO uint32_t W[88];/*!< Word pin registers*/
  __I  uint32_t RESERVED1[1896];
  __IO uint32_t DIR[3];/*!< Port Direction registers*/
  __I  uint32_t RESERVED2[29];
  __IO uint32_t MASK[3];/*!< Port Mask register*/
  __I  uint32_t RESERVED3[29];
  __IO uint32_t PIN[3];/*!< Port pin register*/
  __I  uint32_t RESERVED4[29];
  __IO uint32_t MPIN[3];/*!< Masked port register*/
  __I  uint32_t RESERVED5[29];
  __IO uint32_t SET[3];/*!< Write: Set port register Read: port output bits*/
  __I  uint32_t RESERVED6[29];
  __O  uint32_t CLR[3];/*!< Clear port*/
  __I  uint32_t RESERVED7[29];
  __O  uint32_t NOT[3];/*!< Toggle port*/
} LPC_GPIO_PORT_Type;

[u]LPCopen gpio_11u6x.h include:[/u]
typedef struct {/*!< GPIO_PORT Structure */
__IO uint8_t B[128][32];/*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
__IO uint32_t W[32][32];/*!< Offset 0x1000: Word pin registers port 0 to n */
__IO uint32_t DIR[32];/*!< Offset 0x2000: Direction registers port n */
__IO uint32_t MASK[32];/*!< Offset 0x2080: Mask register port n */
__IO uint32_t PIN[32];/*!< Offset 0x2100: Portpin register port n */
__IO uint32_t MPIN[32];/*!< Offset 0x2180: Masked port register port n */
__IO uint32_t SET[32];/*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */
__O  uint32_t CLR[32];/*!< Offset 0x2280: Clear port n */
__O  uint32_t NOT[32];/*!< Offset 0x2300: Toggle port n */
} LPC_GPIO_T;

Both includes clearly doesn't lead to the same offsets for the W registers. :(

When i calculate the offset address for the W register from the LPCopen include file (128x32=4096=0x1000) it leads to an offset of 0x1000. So now i'm really confused what the real offset is now.

It would be nice if an official could give a statement if it is now 0x100 (Keil-MDK) or 0x1000 (NXP-LPCopen). But clearly one of both seems to be wrong if i haven't made a calculation error.

Ciao,
        Rainer

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Fri Aug 08 17:08:02 MST 2014
Thank you very much Rainer.
I will confirm this issue and modify the user manual. Thanks for reporting.

regards,