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Number of PCLK cycles for CT32Bn_MAT0 pin to change state when a match occurs between the TC and MR0

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by abasak on Fri Mar 11 02:17:17 MST 2016
Hello,

This is with reference to LPC111x series of uC (specifically LPC1114FN28). My question is how many number of PCLK cycles does it have to elapse for CT32Bn_MAT0 pin to change state when a match occurs between the TC and MR0?

In case the timer is configured to generate an interrupt on match, the manual says that interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value. Is it the same for changing the state of CT32Bn_MAT0 pin?

Thanks!
Abhishek

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