lpcware

LPC11xx UART LSR->THRE status

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Charr on Wed Jul 17 01:04:12 MST 2013
Hello everyone,

I start developing with LPC1114 with LPCxpresso board. I encounter some timing problem with UART peripheral (or maybe I do something wrong). Can somebody explain me why LSR->THRE flag stays active for over 1300 while loop cycles described below (for my clock dividers it 1300 is time necessery for one frame to go out from device)? I reather expected that LSR_THRE flag will be cleared automatically by FIFO when data from THR comes into FIFO, but now it looks like LSR_THRE stays inactive (logical "0") until data comes out from device. If that is normal device mode what is real difference beetwen THRE and TEMT flag? I thought that when I put i.e. 10 data bytes into transmit fifo, TEMT stay low until all data comes out from fifo, but THR come back to logical "1" after data will be catched by fifo (Then I could use these flags to get information about fifo full, and LSR_THRE would indicate if I can put next data byte into transmiter )

Compiler optimization is -o0
System Clock           48MHz
AHB divider            0x01
UARTDIV                0x04



#define LSR_THRE 0x20

uint32_t counter =0;
// after device init with UART interrupt disable
UART->THR = 0xaa;

while (!(UART->LSR & LSR_THRE)) {   // while THR has valid data
    counter++;
}



Thank you a lot for response,
Charr

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