lpcware

Bug in LPCOpen - ADC_MAX_SAMPLE_RATE

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by brownm on Mon Oct 20 18:31:22 MST 2014
Hi there

In the LPCOpen 11u68 ADC example named periph_adc

The ADC clock rate is set in main() as follows.

/* Setup for maximum ADC clock rate using sycnchronous clocking */
Chip_ADC_SetClockRate(LPC_ADC, ADC_MAX_SAMPLE_RATE);

In the header file adc_11u6x.h

/** Maximum sample rate in Hz (12-bit conversions) */
#define ADC_MAX_SAMPLE_RATE 50000000                     //<---------------------BADNESS HERE


50MHz is too fast.

The user manual  page 299

Maximum 12-bit conversion rate of 2 Msamples/s (VDD = 2.7 V to 3.6 V) or
1 Msamples/s (VDD = 2.4 V to 2.7 V).

Using 50Mhz causes weirdness all over the place.

Regards
Marshall


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