AN11175 DALI master bus receive

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by purplexed on Thu Jun 26 06:03:10 MST 2014
I was analyzing the AN on the subject and I' ve observed a misaligned information between the schematic of the board and the sample code.
In the schematic, DALI bus reception line is connected on TIMER 0 capture 0 and on TIMER 1 match 0, while the code configures and uses timer1 capture and match channels only.
Capture is used to manage the backward frame, but in this case it seems not to care about it because of the improper configuration; so the application works but responses from dali bus appear as always true because the line can't be sampled.
Am I wrong?