LPC1114 SSP TX FIFO clear

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by romko on Wed Oct 22 01:41:59 MST 2014

I have iplemanted SPI slave device on my LPC1114 processor. My system put data to the SSP TX FIFO on the TXMIS (TX FIFO is at least half empty) interrupt. So it is always "pumping" data to the TX FIFO.
For providing packet integrity I need somehow reset data that already exists in the TX FIFO in case when some error ocured. For now I haven't find better solution than reseting complete SSP peripheral by
LPC_SYSCON->PRESETCTRL &= ~(0x01 << 0);
LPC_SYSCON->PRESETCTRL |= (0x01 << 0);

Is the better way to clear SSP TX FIFO ?