Content originally posted in LPCWare by sinanjj on Wed Nov 27 00:08:09 MST 2013
void spi_init(void)
{
LPC_SYSCON->PRESETCTRL |= (0x1<<0); //reset de-asserted
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<11); //Enables clock for SPI0
LPC_SYSCON->SSP0CLKDIV = 0x01; // Divided by 1. SSP0CLK=Fmain/1=48Mhz
LPC_IOCON->PIO0_8 &= ~0x07; LPC_IOCON->PIO0_8 |= 0x01; // MISO0
LPC_IOCON->PIO0_8 &= ~0x18;
LPC_IOCON->PIO0_9 &= ~0x07; LPC_IOCON->PIO0_9 |= 0x01; // MOSI0
LPC_IOCON->SCK_LOC = 0x00; //Selects SCK0 function in pin location PIO0_10. JTAG DISABLED
LPC_IOCON->JTAG_TCK_PIO0_10 &= ~0x07; LPC_IOCON->JTAG_TCK_PIO0_10 |= 0x02; // SPI CLK0
LPC_IOCON->PIO0_2 &= ~0x07; LPC_IOCON->PIO0_2 |= 0x01; // SPI SSEL0
LPC_SSP0->CR0 = 0x00cf; // data size 16bit, CPOL=1(CLK idle high), CPHA=1, SCR=1
LPC_SSP0->CPSR = 0x2; // SSPCPSR clock prescale register, master mode, minimum divisor is 0x02. Fspi=SPI0CLK/(CPSDVSR*[SCR+1])=48M/(2*(0+1))=24M
LPC_SSP0->CR1 |= (0x1<<1); // Master mode
}
