lpcware

SPI MOSI is idle high

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by emp on Fri Sep 05 06:32:02 MST 2014
Hello,

currently i am building a ws2812 driver using the spi interface of the LPC11C14 (later it should run on a LPC1113).

The user manual on page 234 says "In this configuration, during idle periods: ... The transmit MOSI/MISO pad is in high impedance.". In this configuration means CPOL 0, CPHA 1 in my case. However this sentence is used for every CPOL, CPHA combination.

My Scope shows, that the MOSI line is high in the idle state. I have added an external 10 KOhm Resistor between ground and MOSI (Pull-Down).

Is there something wrong in my initialisation or is this an undocumentent fault? The errata sheet does not mention the spi. A search in this forum and the internet revealed nothing

        //MOSI, No PULL-UP/DOWN, No Hystersis, No Open Drain
        LPC_IOCON->PIO2_3 = (0x02 << 0) | (0x00 << 3) | (0x00 << 5) | (0x00 << 10);
        //SSL1
        LPC_IOCON->PIO2_0 = (0x02 << 0) | (0x00 << 3) | (0x00 << 5) | (0x00 << 10);

        //Hardware init (SSP1)
        LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); //Power

        LPC_SYSCON->SSP1CLKDIV = 1;

        LPC_SYSCON->PRESETCTRL &= ~(1 << 2);    // Reset
        LPC_SYSCON->PRESETCTRL |= (1 << 2);             //Reset end

        //16 Bit Transfer, SPI Mode, CPOL 0, CPHA 1, Serial Clock Rate
        LPC_SSP1->CR0 = (0x0F << 0) | (0x00 << 4) | (0x00 << 6) | (0x01 << 7) | ((SystemAHBFrequency / (5000000 -1)) << 8);
        // No Loopback mode, SPI Disable, Master
        LPC_SSP1->CR1 = (0x00 << 0) | (0x00 << 1) | (0x00 << 2);
        //Clockprescaler to minimal value
        LPC_SSP1->CPSR = 2;

        LPC_SSP1->CR1 |= (1 << 1); //enable spi

I do not need the SCK and MISO Pins. Even SSL is for debugging only.

Thanks emp

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