Content originally posted in LPCWare by NXP_Paul on Fri Sep 06 07:22:06 MST 2013
Have you tried using the IRQLATENCY register to improve the jitter?
From the UM10398 User Manual:
The IRQLATENCY register is an eight-bit register which specifies the minimum number of
cycles (0-255) permitted for the system to respond to an interrupt request. The intent of
this register is to allow the user to select a trade-off between interrupt response time and
determinism.
Setting this parameter to a very low value (e.g. zero) will guarantee the best possible
interrupt performance but will also introduce a significant degree of uncertainty and jitter.
Requiring the system to always take a larger number of cycles (whether it needs it or not)
will reduce the amount of uncertainty but may not necessarily eliminate it.
Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt
request within 15 cycles. System factors external to the cpu, however, bus latencies,
peripheral response times, etc. can increase the time required to complete a previous
instruction before an interrupt can be serviced. Therefore, accurately specifying a
minimum number of cycles that will ensure determinism will depend on the application.