Content originally posted in LPCWare by brattchess on Thu Mar 05 00:52:52 MST 2015
Is it correct this configuration to use the IRC source clock and the clockout of th PLL system will be 12Mhz?
#define SETTINGIRC2\
LPC_SYSCON->SYSAHBCLKDIV = 0x1; /*set clock divider for core to 1*/\
LPC_SYSCON->MAINCLKSEL &= ~(0x03); /*set “main clock” to IRC oscillator, if not system will lock up when PLL turns off!(sec. 3.5.11)*/\
LPC_SYSCON->MAINCLKUEN &= ~(1); /*write a zero to the MAINCLKUEN register (sec. 3.5.12), necessary for MAINCLKSEL to update*/\
LPC_SYSCON->MAINCLKUEN |= 1; /*write a one to the MAINCLKUEN register (sec. 3.5.12), necessary for MAINCLKSEL to update*/\
\
LPC_SYSCON->SYSOSCCTRL = 0x00; \
\
LPC_SYSCON->SYSPLLCLKSEL = 0x00; /*connect IRC oscillator to SYSTEM PLL (sec. 3.5.9)*/\
LPC_SYSCON->SYSPLLCLKUEN &= ~(1); /*write a zero to SYSPLLUEN register (sec. 3.5.10), necessary for SYSPLLCLKSEL to update*/\
LPC_SYSCON->SYSPLLCLKUEN |= 1; /*write a one to SYSPLLUEN register (sec. 3.5.10), necessary for SYSPLLCLKSEL to update*/\
LPC_SYSCON->PDRUNCFG |= (1<<7); /*power down the PLL before changing divider values (sec 3.5.35)*/\
LPC_SYSCON->SYSPLLCTRL = 0x00; /*set MSEL = 0x00011 and PSEL = 0x01 (sec 3.5.3 and table 46 of sec. 3.11.4.1)*/\
LPC_SYSCON->PDRUNCFG &= ~(1<<7); /*power up PLL after divider values changed (sec. 3.5.35)*/\
while((LPC_SYSCON->SYSPLLSTAT & 1) == 0); /*wait for PLL to lock*/\
LPC_SYSCON->MAINCLKSEL = 0x03; /*set system oscillator to the output of the PLL (sec. 3.5.11)*/\
LPC_SYSCON->MAINCLKUEN &= ~(1); /*write a zero to the MAINCLKUEN register (sec. 3.5.12), necessary for MAINCLKSEL to update*/\
LPC_SYSCON->MAINCLKUEN |= 1; /*write a one to the MAINCLKUEN register (sec. 3.5.12)*/
