lpcware

SSP slave RNE bit isn't set but an overrun is received

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by purplexed on Tue Jul 29 04:54:17 MST 2014
Hi everybody.

I'm experiencing a problem with the ssp peripheral in lpc1114 33 pins.
I'm using IAR ssp slave code example listed below (it's extracted the code referring to port 0, the only one involved).
In my application the slave device attemps to receive an expected number of bytes with SSP_Receive() function listed below, but, if data received is over 8 bytes (...same as the ssp fifo buffer...mmmm...), the 9th one doesn't set RNE bit so that the ssp buffer isn't read and the remaining data trigger the overrun interrupt.
Master device transmits at 1,25 MHz and the pheripheral clock is 48 MHz.
I can't understand what's happening. Someone has an idea?
Thank you.

Init function:

#define SSP_SLAVE 1
#define USE_CS       1
#define LOOPBACK_MODE 0

void SSP_IOConfig( uint8_t portNum )
{
 
LPC_SYSCON->PRESETCTRL |= (0x1<<0);
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<11);
LPC_SYSCON->SSP0CLKDIV = 0x2;/* Divided by 2 */
LPC_IOCON->PIO0_8           &= ~0x07;/*  SSP I/O config */
LPC_IOCON->PIO0_8           |= 0x01;/* SSP MISO */
LPC_IOCON->PIO0_9           &= ~0x07;
LPC_IOCON->PIO0_9           |= 0x01;/* SSP MOSI */
#ifdef __JTAG_DISABLED
LPC_IOCON->SCK_LOC = 0x00;
LPC_IOCON->SWCLK_PIO0_10 &= ~0x07;
LPC_IOCON->SWCLK_PIO0_10 |= 0x02;/* SSP CLK */
#else
#if 0
/* On HummingBird/Candiru 1(HB1/CD1), SSP CLK can be routed to different
pins, other than JTAG TCK, it's either P2.11 func. 1 or P0.6 func. 2. */
LPC_IOCON->SCK_LOC = 0x01;
LPC_IOCON->PIO2_11 = 0x01;/* P2.11 function 1 is SSP clock, need to
combined with IOCONSCKLOC register setting */
#else
LPC_IOCON->SCK_LOC = 0x02;
LPC_IOCON->PIO0_6 = 0x02;/* P0.6 function 2 is SSP clock, need to
combined with IOCONSCKLOC register setting */
#endif
#endif/* endif __JTAG_DISABLED */ 

#if USE_CS
LPC_IOCON->PIO0_2 &= ~0x07;
LPC_IOCON->PIO0_2 |= 0x01;/* SSP SSEL */
#else
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);

LPC_IOCON->PIO0_2 &= ~0x07;/* SSP SSEL is a GPIO pin */
/* port0, bit 2 is set to GPIO output and high */
GPIOSetDir( PORT0, 2, 1 );
GPIOSetValue( PORT0, 2, 1 );
#endif

  return;
}

void SSP_Init( uint8_t portNum )
{
  int ii;
  volatile uint8_t Dummy;

/* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
LPC_SSP0->CR0 = 0x0707;

/* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
LPC_SSP0->CPSR = 0x2;

for ( ii = 0; ii < FIFOSIZE; ii++ )
{
  Dummy = LPC_SSP0->DR;/* clear the RxFIFO */
}
   
/* Enable the SSP Interrupt */
NVIC_EnableIRQ(SSP0_IRQn);

/* Device select as master, SSP Enabled */
#if LOOPBACK_MODE
LPC_SSP0->CR1 = SSPCR1_LBM | SSPCR1_SSE;
#else
#if SSP_SLAVE
/* Slave mode */
if ( LPC_SSP0->CR1 & SSPCR1_SSE )
{
  /* The slave bit can't be set until SSE bit is zero. */
  LPC_SSP0->CR1 &= ~SSPCR1_SSE;
}
LPC_SSP0->CR1 = SSPCR1_MS;/* Enable slave bit first */
LPC_SSP0->CR1 |= SSPCR1_SSE;/* Enable SSP */
#else
/* Master mode */
LPC_SSP0->CR1 = SSPCR1_SSE;
#endif
#endif
/* Set SSPINMS registers to enable interrupts */
/* enable all error related interrupts */
LPC_SSP0->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM;

  return;
}


Interrupt handler:

void SSP0_IRQHandler(void)
{
  volatile uint32_t regValue;

  regValue = LPC_SSP0->MIS;
  if ( regValue & SSPMIS_RORMIS )/* Receive overrun interrupt */
  {
interruptOverRunStat0++;
LPC_SSP0->ICR = SSPICR_RORIC;/* clear interrupt */
  }
  if ( regValue & SSPMIS_RTMIS )/* Receive timeout interrupt */
  {
   
interruptRxTimeoutStat0++;
LPC_SSP0->ICR = SSPICR_RTIC;/* clear interrupt */
  }

  /* please be aware that, in main and ISR, CurrentRxIndex and CurrentTxIndex
  are shared as global variables. It may create some race condition that main
  and ISR manipulate these variables at the same time. SSPSR_BSY checking (polling)
  in both main and ISR could prevent this kind of race condition */
  if ( regValue & SSPMIS_RXMIS )/* Rx at least half full */
  {
interruptRxStat0++;/* receive until it's empty */
  }
  return;
}


Receive function:

void SSP_Receive( uint8_t portNum, uint8_t *buf, uint32_t Length )
{
  uint32_t i;
 
  for ( i = 0; i < Length; i++ )
  {
/* As long as Receive FIFO is not empty, I can always receive. */
/* If it's a loopback test, clock is shared for both TX and RX,
no need to write dummy byte to get clock to get the data */
/* if it's a peer-to-peer communication, SSPDR needs to be written
before a read can take place. */

#if !LOOPBACK_MODE
#if SSP_SLAVE
        while ( !(LPC_SSP0->SR & SSPSR_RNE) );
#else
  LPC_SSP0->DR = 0xFF;
  /* Wait until the Busy bit is cleared */
  while ( (LPC_SSP0->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
#endif
#else
  while ( !(LPC_SSP0->SR & SSPSR_RNE) );
#endif
  *buf = LPC_SSP0->DR;
  buf++;

  }
  return;
}

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