lpcware

LPC4337JBD144E & 48LC32M16A2

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by GooglyFace on Thu Aug 14 13:42:11 MST 2014
Hello,
    I am using an LPC4337JBD144E (144pin) in our custom module. The SDRAM is a single Micron 48LC32M16A2. The pin connections are

EMC_D[0~15] to DQ[0~15]
EMC_A[0~12] to A[0~12]
EMC_A13    to BA0
EMC_A14    to BA1
EMC_DQMOUT0 to DQML
EMC_DQMOUT1 to DQMH
EMC_WE    to WE
EMC_CAS     to CAS
EMC_RAS     to RAS
EMC_CLKOUT0 to CKE
EMC_CLK0    to CLK ( Can switch to CLK2 using jumper )
GND         to CS  ( Driving a single chip )


   I have been to other similar SDRAM topics in forums already. My question is what should be the following register settings for the EMC controller if I am running a dual core application @192Mhz with EMC clock of 96Mhz.


CLK_M4_EMC_DIV
CLK_M4_EMC
EMCDELAYCLK
DYNAMICRASCAS0    // SHOULD BE ABLE TO USE CL=2
DYNAMICREFRESH           
DYNAMICREADCONFIG
DYNAMICRP
DYNAMICRAS
DYNAMICSREX
DYNAMICAPR
DYNAMICDAL
DYNAMICWR
DYNAMICRC
DYNAMICRFC
DYNAMICXSR
DYNAMICRRD
DYNAMICMRD

    I am setting the As per manual my mode register should be 0x23. I am using either
"address mapping" of 0x11 for mode offset of 13 ( i.e, RBC MODE: 0x28046000 )
    or  "address mapping" of 0x31 for mode offset of 11 ( i.e, BRC MODE: 0x28011800 )

    I set CREG6 at the same time CLK_M4_EMC_DIV & CLK_M4_EMC are set. I know if I use the Micron values I get hard faults. I think the above information might be useful for other people also.

Thanks,
D.G.

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