LPC1114FN28/102 Flash controller documentation and ECC algorithm

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by m-atthias on Sat Nov 08 11:06:45 MST 2014
Dear LPC geeks,

I am happy to announce an experimental port of Mecrisp-Stellaris, a standalone native code Forth, for the breadboard friendly, DIP28 packaged LPC1114FN28/102. But this one has a tricky Flash IAP interface with 256 bytes write and 4 kb erase block size. The datasheet indicates that there is an ECC checksum over each 16 bytes which should be writeable separately, but unfortunately, I could not find ECC algorithm or Flash controller register documentation. If you know details, you could save me from disassembling and understanding the internal Boot ROM which contains the big-block in-application-flash-write code. Directly manipulating ECC or calculating ECC-adaption fill bytes could give very small individual writes needed for direct Flash compilation.

Best wishes from Germany,