Trouble with building dual-core - blink example - LCP4330-xplorer board

[lpcware]

Content originally posted in LPCWare by Witte on Thu Jul 31 11:07:01 MST 2014
Hello there,

I'm studing now the LCP4337 with the LCP4330-xplorer board.

I will using the IAR to develop my code, so I download some examples by NXP. Follow the link: http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc43xx-packages

I tried building the examples NGX Xplorer LPC4330 board (with a LPC4337) v2.12 and v2.09, but nothing works. Always I building the example "sa_blinky-spifi_ngx_xplorer_4330" I got this error:

"Fatal Error[Li001]: could not open file "C:\Users\Quadrar\Desktop\LCP Open v2.09 - IAR - NGX Xplorer 4330\software\lpc_core\lpc_board\boards_43xx\ngx_xplorer_4330\
iar_output\ngx_xplorer_4330\Exe\lib_lpc_board_ngx_xplorer_4330.a"
Error while running Linker "

I checked the directory and really doesn't have the archive.
I tried with another examples and I got the same error.

So I did this with LPXpresso IDE, and I get the same error, the archive could not be found.

What can I do to fix this?

Thanks for support.

[lpcware]

Content originally posted in LPCWare by Witte on Thu Aug 21 12:57:41 MST 2014
Hi nerd herd and mc,

Is working!

Well I found a example in IAR IDE with HITEX board, this board use a LPC4350.
In the example the project run in SRAM, Flash and SPIFI (external Flash).

The big point were in the ".icf" and ".mac" file. (attached)

The file ".icf" are the address of SRAM, RAM and others. Another important point in the file ".icf" we found the linker between Core M0 and Core M4 binaries.

The file ".mac" set the memory region to write the binarie linked in External Flash Memory.
The address is 0x14000000.

To debug we need follow some steps:
- Make the project Cortex M0. The binary from Core M0 will be created.
- Make the project Cortex M4. At this point the project M4 will join the two binary files.
- Hit the button "Debug and Download" on the project M4.
- Hit the button "Debug without Download" on the project M0. We need this just to JTAG probe connect on the Cortex M0.

After that I could control both Cortex M.

I attached the project too.

Thanks for the support and time!

[lpcware]

Content originally posted in LPCWare by Witte on Thu Aug 21 06:51:28 MST 2014

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Quote: nerd herd
If you look at the memory map for flashless parts in the LPC43xx user's manual, section 4.3, you have two memory regions for SPIFI data: 0x8000 0000 - 0x8800 0000 and 0x1400 0000 - 0x1800 0000.

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Nerd Herd, I'm sorry, was a typo... I'm using the LPC4330-Xplorer Board, and this KIT use a LPC4337JET100.
I created two ".board" files with the address 0x8000 0000 - 0x8800 0000 and 0x1400 0000 - 0x1800 0000, but doesn't works either.
The memory in this KIT is S25FL032P0XMFI013.

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Quote: mc
Keil MCB4300 board contains LPC4357 and your board has LPC4337. There is no difference between LPC4337 and LPC4357 in term of flash size and type. The difference is LPC4357 can have more peripherals including LCD peripheral and some packages of LPC4337 don't.

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MC, Where can I find the file you mentioned?

Thanks guys and sorry the delay to reply.

[lpcware]

Content originally posted in LPCWare by nerd herd on Tue Aug 19 10:33:24 MST 2014
Hi mc,

For some reason it did not click to me that he said LPC4337 in his post, which would definitely be a flash part.

Witte, was the post about using the LPC4337 a typo? From your logs and previous posts, you seem to be using the NGX Xplorer 4330 board with an LPC4330, a flashless part.

[lpcware]

Content originally posted in LPCWare by mc on Tue Aug 19 10:00:00 MST 2014
Hi Witte,

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Quote:
In my case I'm using the LPC4337, this part number doesn't have internal flash, just an external flash memory SPIFI interface. Can I use the file "FlashNXPLPC18xx_1024K.board" in this case?

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Keil MCB4300 board contains LPC4357 and your board has LPC4337. There is no difference between LPC4337 and LPC4357 in term of flash size and type. The difference is LPC4357 can have more peripherals including  LCD peripheral and some packages of LPC4337 don't.

So you can use same flash driver for LPC4357 and LPC4337.

[lpcware]

Content originally posted in LPCWare by nerd herd on Tue Aug 19 09:32:00 MST 2014
Hi Witte,

Unfortunately, I do not have access to a LPC4337 development board, but your hunch is correct. You just need to flash to the correct memory address, and the memory addresses I told you to flash were incorrect. If you look at the memory map for flashless parts in the LPC43xx user's manual, section 4.3, you have two memory regions for SPIFI data: 0x8000 0000 - 0x8800 0000 and 0x1400 0000 - 0x1800 0000. I would program one core with one memory region and program another with the other. So what I would do is to take any .board file and create my own two .board files each with one of these memory regions. Let me know if it works!

Link to the user's manual:
http://www.nxp.com/documents/user_manual/UM10503.pdf

[lpcware]

Content originally posted in LPCWare by Witte on Tue Aug 19 07:25:17 MST 2014
Hey nerd Herd,

No problem man, thanks for your support and time!

Well, I did all the steps and get the follows results:
- When I run any instance to debug I get this message: "There were warnings while generating flash loader input. See the Debug Log window for details."
- After this, an other warning appear: "Stack pointer is setup to incorrect alinment. Stack addr = 0xAAAAAAAA".
- I attached my debug logs: "Log_M4.txt" and "Log_M0.txt". (I hope it helps)

In my case I'm using the LPC4337, this part number doesn't have internal flash, just an external flash memory SPIFI interface. Can I use the file "FlashNXPLPC18xx_1024K.board" in this case?

After run the debug in both instances of IAR, I just could control the Core M4. The LED blinked, but without the full debug with Core M0 it's difficult design.

Let me know if you have more tips for this issue.
Thanks again nerd Herd!
Bye!

[lpcware]

Content originally posted in LPCWare by nerd herd on Mon Aug 18 16:10:00 MST 2014
Hi Witte,

Sorry for the wait, this took a bit of time to dig up the right configurations for IAR. Tell me if this works for you or not...I think I managed to debug both cores but I'm using LPCOpen 2.12 with a Keil MCB4300 development board.

1) Download and extract the latest LPCOpen 2.12 software platform. Open the dual core IAR project.
2) Like we discussed earlier in the thread, compile the four libraries.
3) Right click the M4 blinky example and click options. Click Debugger in the categories on the left pane.
4) In the Setup tab, make sure you have the right debugger chosen under "driver" (default is I-jet/JTAGjet).
5) In the Download tab, make sure "Use flash loader(s)" and "Override default .board file" are the only boxes checked.
6) Make sure the current .board file chosen is "$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC18xx_1024K.board". Click edit and delete bank B from the .board file. Click ok to save as a new .board file.
7) Now right click the M0 blinky example and click options. In the "General Options" category in the left pane, change the processor variant from device to Core (and Core should be Cortex-M0; this was the hardest part figuring out why IAR wouldn't flash the M0 core correctly -- the "NXP LPC4357_M0" device file indicates there is no flash for some reason).
8) Repeat steps 4-7 for the M0 options except delete bank A from the .board file and save that as it's own .board file. This way bank A will contain the M4 code while bank B contains M0 code and they won't accidentally flash over each other's code.

After these steps, I was able to debug both cores independently on different IAR instances. I'm not sure if I was able to stop one core while the other one was going, but that would be an IAR/debugger limitation and I won't be able to help much with that. Also, I believe the dual core blinky code resets the M0 core so you might get a pop up in the M0 debugging session that it has lost it's connection. Hope this helps!

[lpcware]

Content originally posted in LPCWare by Witte on Thu Aug 14 12:52:15 MST 2014

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Quote: nerd herd
Hello,

I'm currently looking into debugging both cores. I know it is possible to do so on the Keil IDE and our own LPCXpresso, but IAR has given us problems before. Also, the blinky m0 project seems to have its own issues as I get the same stack pointer error and I am unable to simply download the code. I'll look into debugging both cores on IAR but would you be willing to use a different IDE? Keil would be best for me to walk you through it.

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Unfortunately not, because the IAR is the official IDE in the company where I work. I'm glad if you can help me with IAR. Tell me what I need do and I execute here.

Thanks very much!

[lpcware]

Content originally posted in LPCWare by nerd herd on Thu Aug 14 12:19:00 MST 2014
Hello,

I'm currently looking into debugging both cores. I know it is possible to do so on the Keil IDE and our own LPCXpresso, but IAR has given us problems before. Also, the blinky m0 project seems to have its own issues as I get the same stack pointer error and I am unable to simply download the code. I'll look into debugging both cores on IAR but would you be willing to use a different IDE? Keil would be best for me to walk you through it.

[lpcware]

Content originally posted in LPCWare by Witte on Thu Aug 14 07:04:31 MST 2014
Hey, thanks for your help...

Like you say, I followed this steps and everything worked well...

But now I can't debug both core M4/M0.
I followed this steps:
- I opened a IAR instance with "sa_blinky - spifi_ngx_xplorer_4330";
- I opened the second IAR instance with "sa_blinky_m0 - spifi_ngx_xplorer_4330";
- In the first instance I download the m4 project into the flash memory;
- In the second instance I run the debug, after this I received this message "Warning: Stack pointer is setup to incorrect alignment. Stack addr = 0xFFFFFFFF". When the window changed to debug view, the stack pointer is in address 0xFFFFFFFE.
- I returned to the first instance and run the debug.
- When I tried set a breakpoint or pause the Core M0 doesn't worked. Only in the core M4 I could do this.

I'm using the Segger JTAG. Is there any configuration or step I did wrong or forget?

Thanks for your support nerd herd!

[lpcware]

Content originally posted in LPCWare by nerd herd on Thu Jul 31 12:34:00 MST 2014
Hello,

To build the exampes from LPCOpen, be sure to compile the necessary libraries and have them included in the project you want to run. For instance, to run the dual core blinky example, open the dual core project and compile the top four projects, starting with "lib_lpc_chip_43xx-chip_43xx_lib" and ending with the fourth library named "lib_lpc_board_ngx_xplorer_4330_m0-ngx_xplorer_4330". The reason is because you need a library for the chip and the board, per core. Since you're interested in a dual core example, you'll need to compile a chip and board library for each. That will generate the necessary file that the linker is looking for. Hope that helps.

EDIT: I didn't see your second post. Correct, that link will tell you what you need to know. But keep in mind that these kind of libraries will need to be compiled for any IDE, not just IAR.

[lpcware]

Content originally posted in LPCWare by Witte on Thu Jul 31 12:32:10 MST 2014
Hey... I found the "problem"...

I didn't see this link: http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-microcontrollers/lpcopen-v200-quicks...

First of all, who wants building with IAR needs build the libraries.