lpcware

LPCOPEN 2.XX and EMC Setup for flash-less parts!

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by vostro1000 on Mon Dec 23 13:32:57 MST 2013
Hi! I'am using a board with LPC4350 and one 16 bit external flash (the only non  volatile memory that Ihave in the board)... Using one example that uses old libraries I'am able to config the clock with sucess! But the new ones (lpcopen 2.XX ) give a hard fault! I tried to adapt the 1.3 part of the code but without sucess... Can any one give me a hint?

old ram setup 1.3


  div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
   //  LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;
   //  LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2
   //  while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));

     /* This code configures EMC clock divider and is executed in RAM          */
         for (n = 0; n < emcdivby2_szw; n++) {
           emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
           *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_op1 + n);
         }
         __ISB();
         ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
         for (n = 0; n < emcdivby2_szw; n++) {
           *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
         }




My one:


div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
   //  LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;
   //  LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2
   //  while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));

     /* This code configures EMC clock divider and is executed in RAM          */
         for (n = 0; n < emcdivby2_szw; n++) {
           emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
           *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_op1 + n);
         }
         __ISB();
         ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLKCCU[CLK_MX_EMC].CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
         for (n = 0; n < emcdivby2_szw; n++) {
           *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
         }


Part of the function for both.


volatile uint16_t emcdivby2_op1[] =  {
0x6803,        //      LDR  R3,[R0,#0]      ; Load CREG6
0xF443,0x3380, //      ORR  R3,R3,#0x10000  ; /*Set Divided by 2
0x6003,        //      STR  R3,[R0,#0]      ; Store CREG6
0x600A,        //      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg
0x684B,        // loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT
0x07DB,        //      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0
0xD0FC,        //      BEQ  loop            ; Jump if 0
0x4770,        //      BX   LR              ; Exit
0,
};

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