LPCOPEN 2.XX and EMC Setup for flash-less parts!

[lpcware]

Content originally posted in LPCWare by vostro1000 on Mon Dec 23 13:32:57 MST 2013
Hi! I'am using a board with LPC4350 and one 16 bit external flash (the only non  volatile memory that Ihave in the board)... Using one example that uses old libraries I'am able to config the clock with sucess! But the new ones (lpcopen 2.XX ) give a hard fault! I tried to adapt the 1.3 part of the code but without sucess... Can any one give me a hint?

old ram setup 1.3

  div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
   //  LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;
   //  LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2
   //  while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));

     /* This code configures EMC clock divider and is executed in RAM          */
         for (n = 0; n < emcdivby2_szw; n++) {
           emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
           *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_op1 + n);
         }
         __ISB();
         ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
         for (n = 0; n < emcdivby2_szw; n++) {
           *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
         }

My one:

 div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
   //  LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;
   //  LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2
   //  while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));

     /* This code configures EMC clock divider and is executed in RAM          */
         for (n = 0; n < emcdivby2_szw; n++) {
           emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
           *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_op1 + n);
         }
         __ISB();
         ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLKCCU[CLK_MX_EMC].CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
         for (n = 0; n < emcdivby2_szw; n++) {
           *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
         }

Part of the function for both.

volatile uint16_t emcdivby2_op1[] =  {
 0x6803,        //      LDR  R3,[R0,#0]      ; Load CREG6
 0xF443,0x3380, //      ORR  R3,R3,#0x10000  ; /*Set Divided by 2
 0x6003,        //      STR  R3,[R0,#0]      ; Store CREG6
 0x600A,        //      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg
 0x684B,        // loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT
 0x07DB,        //      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0
 0xD0FC,        //      BEQ  loop            ; Jump if 0
 0x4770,        //      BX   LR              ; Exit
 0,
};

[lpcware]

Content originally posted in LPCWare by vostro1000 on Fri Dec 27 05:14:34 MST 2013
In my case is not possible to use spifi interface because one line of the spifi is used by external nor flash.... My problem is not relative with boot but with emc settings for non flash based parts because I want to use also external sdram but first I need to setup external nor flash... But till now no joy! When the code enter in this function

"((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);" the system give me hard fault pn registers it points to "I bus fault"...

I don't have problems with other clocks it seems to work fine and also with code size the actual code is less than 16KB.

This same code works with cmsis old libraries but with new ones for me is not possible!

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Dec 26 13:20:42 MST 2013
Well, I think I know ;-)

The LPCOpen packages do not include examples for LPC4350 running from external flash. But of course this doesn't mean that it is not possible.
The older PDL libraries contain code for this configuration.
There is another non volatile memory on the board, a quadSPI flash which can be used as program memory. The LPC4300 has a so called SPIFI (SPI flash interface) which maps this serial memory into the memory map of the ARM core, so for the ARM it's simply an addressable memory. LPCOpen contains examples for the internal flash (LPC4357) and the SPIFI. The performance of the quadSPI is at least as good as the performance from the external NOR flash, that's why it moved a little bit into the background.

For the external flash you need to consider the following things:

1)  When you start with the bootmode for the external flash, only a limited number of address pins are set up from the bootcode. It lasts for 16kbytes of code. So if you jump into a memory area > 16kbytes you need to set up more address pins before. I do this normally right in the startup.s file, then this is not longer a problem.
2)  The bootcode sets the PLL to 96MHz, you need about 9 waitstates for this frequency. If you set the frequency to e.g. 204MHz you need to increase the waitstates before, otherwise you run immediately into a crash.
3)  The code you use is from a Keil example, this works fine in principle, so if you take care that you port everything correctly, then it should work. Take care that the code in the array is in an area which is not cleared or reused by the linker, but I think this is easy to check with a debugger. Simply step into the code and look if there is something useful. And maybe you also see the point where it crashes.

Hope this helps a little bit.

[lpcware]

Content originally posted in LPCWare by vostro1000 on Thu Dec 26 12:08:09 MST 2013
Nobody knows howto setup emc when booting from external nor flash?