SDRAM reads corrupted while LCD active.

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

SDRAM reads corrupted while LCD active.

318 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by suckfish on Sat Dec 22 16:07:55 MST 2012
Hi,

I've got a problem with SDRAM reads from the CPU getting corrupted while driving a LCD from SDRAM.  Any ideas?

My first guess is a timing problem with the memory accesses, but I really don't have much of a clue how to debug this.

This is a custom board with LPC4357 and a 256Mb 16-bit SDRAM.  The display is 1024 by 640 TFT, 52.25MHz pixel clock.  I get the problem both in 16bpp and 8bpp modes.  The CPU and SDRAM are running at 96MHz.

The display output appears rock solid; no glitches.

The M4 CPU is running test code that reads and writes test patterns; it shows no problems without the LCD running, but with the LCD running it starts showing errors.

My first guess was that I was running out of SDRAM bandwidth, but reducing from 16bpp to 8bpp appears to make no difference.

The memory test code is just:

    volatile unsigned * const sdram = (v32 *) 0x60000000;
    for (int i = 0; i != size; ++i)
        sdram = i * 0x02030401;

    putchar ('\n');
    for (int i = 0; i != size; ++i) {
        unsigned e = i * 0x02030401;
        unsigned v = sdram;
        if (v != e)
            printf ("Memtest: Bugger @ %06x expect %08x got %08x\n",
                    i, e, v);
    }

Cheers,
Ralph.
Labels (1)
0 Kudos
1 Reply

288 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by suckfish on Sat Dec 22 20:02:20 MST 2012
Despite not having a clue I managed to solve it myself...  I was initialising the sdram controller after then lcd controller.  Which meant that the sdram controller was not idle whilst being configured... fixing that has everything working beautifully.
0 Kudos