LPC4370 Dual Core Boot

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LPC4370 Dual Core Boot

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by damihuang on Sat Apr 09 23:27:06 MST 2016
Hi, NXP Support Team,

We are using LPC4370's M4 and M0s cores, we could download and debug using JTAG, now we care about how to boot from USB for both M4 and M0s cores using DFUSec:

1.  After compile the projects, we get two BIN files for M4 and M0s respectively, do we need to combine both file into one file for the DFUSec?

2. If it's not possible to use DFUSec, we could use onboard SPIFI flash, how to set up then? Do you have a detail document for this?

Frank   
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lpcware
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by bavarian on Mon Apr 11 03:38:55 MST 2016
It all depends on how you want to run the software for these two cores. The only non-volatile program memory on the LPC4370 board is the quadSPI (SPIFI), so this most likely needs to be used somehow. The other option is to download code images to internal SRAM and execute it from there, using JTAG/SWD, serial download or DFU mode.

In reality it will be a mix of both, The code images resides in the SPIFI flash:

- M4 executes from SPIFI and M0a and M0s executes from internal SRAM
or
- or the M4 executes from internal SRAM and the M0a executes from SPIFI flash

In theory both cores M4 andf M0a could execute from the SPIFI flash, but then you will experience a significant performance loss as there will be a lot of bus sharing for the two cores.

What needs to be done:
[list]
  [*]  the software for all cores needs to be linked for running from their respective memory areas: M4 code is linked to 0x1400 0000, M0y code is linked to 0x2000 0000 and M0s code is linked to 0x1800 0000 (just one possible setup).
  [*]  the code for the M0a and M0s needs to be put somehow into the M4 project (e.g. as byte array) in order to link it into the M4 image as const data
  [*]  as the M4 is the core running after reset, it needs to manage the relocation of the M0a and M0s code into their SRAM areas and prepare these cores to start (stack pointer and IRQ  vector table settings. You need to manage this manually, the toolchain can't do this for you. This is normally done somewhere in your system init code.
  [*]  there should be some example code for dual core usage in the LPCOpen package for the LPC4300, usage of the third core the M0s is a little bit "less in the focus"  ;-)
[/list]

Regards,
NXP Support Team.
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