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LPC4357, Use SPIFI at high clock , change of latency required

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by peaksystem on Fri Jun 03 04:45:32 MST 2016
Hello,

I use SPIFI Flash  (Spansion S25FL132, which is very similar to the already supported S25FL164) for code execution. This works fine, SPIFI clock is set to (200MHz/3)=66.67MHz.
Now I would like to increase the performante and set to clock to (200MHz/2)=100MHz and use the continuous read mode. SPI-Flash supports up to 108MHz.
This is where my problem starts:
Per default the max. frequency of SPI-Flash is limited to 78MHz in Quad I/O mode. For higher clock rates it is required to increase the Latency Control in the SR3 register.
I can increase the latency of the SPI-Flash to the desired value and this woks (checked with an oscilloscope that the data appear 2 clocks later than before). But is is also required to tell the SPIFI controller that data will arrive 2 clocks later. But it seems that at the point where I modify the latency I cannot change the SPIFI controller registers any more. Could someone give me an advice how to do this (reconfigure SPI-Flash and reconfigure SPIFI controller) in the correct order?


Problem with writing the latency bits:
I found the following code in spifili_fam_standard_cmd.c

/* Disable variable read latency */
if (init) {
status = pHandle->pFamFx->devGetStatus(pHandle);
status &= ~(0xf << 16);/* Latency control bits for this part */
pHandle->pFamFx->devSetStatus(pHandle, status);
}

devSetStatus is set to function
spifiDeviceDataSetStatusS25FL164K

It seems that this code does -NOT- clear the latency control bits in SR3. Function devSetStatus uses command 06h (Write enable), but to change the latency control bits command 50h (Write Enable for Volatile Status Register) is required.

Thank you.

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