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SGPIO + parallel interface

Question asked by lpcware Employee on Jun 15, 2016
Latest reply on Oct 16, 2016 by atsuyo sano
Content originally posted in LPCWare by JMRouxel on Tue Jan 06 01:19:40 MST 2015
I'm working on the LP4350 part. I'm trying to use SGPIO to configure FPGA with parallel 8-bits data. It's the first time I try to use SGPIO and it seems a little confused for me for the moment.

So, to begin with SGPIO, I'm starting my tests from the following example : SGPIO_spi_master from the library lpc43xx.
This example emulates a SPI master (CLK, CS, MISO and MOSI). I can see the different signals on a scope (the clock for example).
My goal is to change the MOSI signal data (which is using just a SGPIO) to a parallel 8-bits data (with the use of 8 SGPIO)

First, when I modify the bits PARALLEL_MODE of the SLICE_MUX_CFG register (shift 1 bit per clock -> 1 byte per clock), I can't see the clock on my scope any more.
I assume that other parameters must be changed, but which?

Can anyone help me?