LPC4337 not programming

[lpcware]

Content originally posted in LPCWare by avr458 on Wed Feb 06 17:43:21 MST 2013
I designed a custom PCB based around the LPC43xx TQFPT144 package. The chip that is populating my PCB is the LPC4337JBD144. I am using a LPC-Link with LPCXpresso. I keep getting the error LPC-Link 1.1 timed out. Are there some crucial steps that I am missing when setting up to program this chip? I have a LPCXpresso project configured for the LPC4337 that successfully compiles all the paths and symbols are set up the MCU settings are configured for the LPC4337 as well as the JTAG and debug settings. Both release and debug are setup the same way so its not that problem. Any ideas?

This is my design
http://www.mediafire.com/?j0062czaai1oaul

[lpcware]

Content originally posted in LPCWare by Alex on Mon Mar 11 05:42:59 MST 2013
Did you take a look to TDI and TCK?

Maybe you can solder small wires directly to the pins of the processor and connect your probes to these wires.

[lpcware]

Content originally posted in LPCWare by avr458 on Sun Mar 10 16:31:17 MST 2013
I have spoken with NXP support they have no idea what is wrong. Recently got this error when trying to erase the chip via LPCXpresso

Pc: (  0) Reading remote configuration
Ni: LPCXpresso Debug Driver v4.0 (Sep 19 2012 09:12:59)
Nc: Looked for chip XML file in /Applications/lpcxpresso_4.3.0_1033/lpcxpresso/bin/LPC4337.xml

Nc: Looked for vendor directory XML file in /Applications/lpcxpresso_4.3.0_1033/lpcxpresso/bin/nxp_directory.xml

Nc: Found generic directory XML file in /Applications/lpcxpresso_4.3.0_1033/lpcxpresso/bin/crt_directory.xml

Pc: (  5) Remote configuration complete
just before: libusb_claim_interface
BytesInQAtOpen = 0
Pc: ( 30) Emulator Connected
Pc: ( 40) Debug Halt
Pc: ( 50) CPU ID
Nc: Emu(0): Conn&Reset. DpID: 2BA01477. Info: LPCLINK
Nc: SWD Frequency: 150 KHz. RTCK: False. Vector catch: False.
Nc: Packet delay: 0  Poll delay: 0.
Nc: Loaded LPC18x7_43x7_2x512_BootA.cfx: LPC18x7/LPC43x7 Flash 2x512KB @0x1A000000 (Boot Bank A) Aug 17 2012 00:15:43  On-chip Flash Memory

Nc: NXP: LPC4337  Part ID: 0x00000000
Pc: ( 65) Chip Setup Complete
Nt: Connected: was_reset=true. was_stopped=false
Cr:v Registered license, download limit of 128K
Pc: ( 70) License Check Complete
Nt: Mass Erase
Ed:04: Failed to erase flash: Ee(07). Bad ACK returned from status - wire error.
Pc: (100) Target Connection Failed

[lpcware]

Content originally posted in LPCWare by Alex on Thu Mar 07 06:34:31 MST 2013
Hi,

I'm using a Segger J-Link as debug probe and IAR as development environment.
The J-Link comes with a license for the J-Flash software which allows to read and write the flash.

I don't know if it is possible to do that with the NXP software. But the fact that no JTAG target is found leads to the conclusion that it is not a software issue.

First of all you should take a look at TCK and TDI. You should see short pulses on TDI when you try to access the 4337 via JTAG. How do these pulses look like?

Is it a commercial project?
Maybe you should try to contact the NXP support directly.

Regards,
Alex

[lpcware]

Content originally posted in LPCWare by avr458 on Tue Mar 05 09:25:25 MST 2013
I am using LPCXpresso with an example project and library built for the LPC4337 that NXP sent to me.I am using the LPC-Link JTAG provided to me by NXP. I do have a scope, I have looked at the crystal and although I can't attach the probe, (hard to attach to SMD solder joints) if I tap the solder joint with the probe I get the 12MHZ signal of the crystal. I haven't yet tried looking at the JTAG signals. As far as reading the FLASH on the LPC4337 am I able to do that with LPCXpresso? As far as it being a layout issue I have attached a PDF of my schematic and PCB design that includes a composite of the board and individual layers.

Some Notes about the PCB:
I have modified the PCB with the following:
- 10K pullup resistors on the pins of the JTAG connector
- DBGEN pulled high with a 10K pullup
- TRST pulled low with a 10k pullwdown

What pins on the JTAG should I test? Right now I'm getting the error that no JTAG targets are found.

[lpcware]

Content originally posted in LPCWare by Alex on Tue Mar 05 01:16:14 MST 2013
My LPC4337 design works quite well using TRST on the JTAG connector. But you are right, according to the user manual using the reset pin should work too.

If it is not the schematic, maybe its a layout issue. Have you been checking the JTAG signals using an oscilloscope?

Do you have an example project that is preconfigured for the LPC4337 and the JTAG adapter you are using?
Maybe you can try it to test JTAG configuration. Even if the example is not able to run it may show if the configuration is the problem.

Also do you have a software you can use to connect to the device via JTAG and read the FLASH of the LPC4337?

[lpcware]

Content originally posted in LPCWare by avr458 on Mon Mar 04 01:49:30 MST 2013
TRST on all the dev boards (Hitex/Keil) use a jumper and have Reset connected to the JTAG. This configuration is used for the 10 pin Cortex Debug connector.
http://www2.keil.com/coresight/coresight-connectors/

The schematic here fits with the eval boards I mentioned above, I have since modified my rev one PCB with the pullups on the JTAG connector, pulled the TRST low, and pulled the DBGEN pin high with a 10K pullup resistor.

[lpcware]

Content originally posted in LPCWare by aras on Tue Feb 26 09:00:40 MST 2013
I have had trouble too...

TRST can float or be pulled-UP (it has an internal PU) and should be high during debug, not low. The DGBEN pin has no internal pull up and should have one fitted or tied off high.

What ever you do, the interface and debugger tools are universally flaky to say the least. You will probably need a power-cycle both on your board and on the USB Xpresso debugger from time to time!

Cheers, Richard.

[lpcware]

Content originally posted in LPCWare by Alex on Tue Feb 26 01:28:27 MST 2013
Hi,

did you connect TRST to the JTAG header?

I can see three different connectors for JTAG debug TRST. How are they used?
Why is RESET connected to the debug header and not TRST?

Regards,
Alex

[lpcware]

Content originally posted in LPCWare by avr458 on Mon Feb 25 01:26:24 MST 2013
I have modified my existing PCB with a 10K pullup on the DBGEN and a 10K pulldown on the TRST pin. The device is still not programming this is the project I am using:
http://www.mediafire.com/?bcze99ox053j51j

I build the project from the sources found in the current release of the LPCOpen library, everything compiles without errors but I am still unable to flash the binary onto the LPC4337JBD144. I am no longer getting the LPC-Link timeout error but instead it is telling me that the target is not debug enabled, in this case it clearly is since I have added the pullup and pulldown resistors as specified in the diagram provided in the above post. I haven't added pullups on the JTAG as I don't know how I can get them on to the PCB, could that be causing the problems?


BTW here is the finalized version of my new design slated to go out to the fab house on Monday. I have made all the modifications that I was instructed to do so in the above posted schematic. Will these changes guarantee me a programming board?

http://www.mediafire.com/view/?yuchlc56wdcxu69

Please get back to me as soon as you can.

[lpcware]

Content originally posted in LPCWare by avr458 on Mon Feb 18 01:54:27 MST 2013
Thanks for your detailed response. So if I update my design exactly like this I should be able to program with the JTAG just fine? I will try modifying my 1st revision PCB with thin wires and resisters to test it. Also what is the value on the TRST resistor? 10k like everything else?


Also should the JTAG pullups be close to the JTAG header or the LPC4337 ? Same goes for the ESD circuit.

EDIT:

I have uploaded the finished revised design here
http://www.mediafire.com/?rfn3p60nfr85s53

please let me know if I need to make any additional changes

[lpcware]

Content originally posted in LPCWare by bavarian on Wed Feb 13 03:20:00 MST 2013
Most of the things are already discussed in the thread.

Please look into the attachment for a schematic of the 10-pin debug connector.
The ESD protection is useful for development boards, we have seen setups where switched power supplies for the board had a huge potential difference to the power supply level of the JTAG debugger box. This could destroy the input of the LPC43xx.

Your problem with the LPCLink might be on the LPCLink side and not on your connector design.
But according to Code Red it should work fine:  http://support.code-red-tech.com/CodeRedWiki/LPC1850_4350_Support

Best regards,
NXP Technical Support

[lpcware]

Content originally posted in LPCWare by avr458 on Mon Feb 11 09:17:09 MST 2013
Anyone got any ideas? I need to update my second revision and get it ordered in the next few days so this is time sensitive.

[lpcware]

Content originally posted in LPCWare by avr458 on Fri Feb 08 17:56:50 MST 2013
This is how I setup my JTAG header
http://www.keil.com/support/man/docs/ulinkpro/ulinkpro_hw_if_jtag10.htm

It appears that I need to pull the DBGEN and TRST pins high with pullup resisters, is that correct?

[lpcware]

Content originally posted in LPCWare by avr458 on Fri Feb 08 16:17:06 MST 2013
So DBGEN needs to be pulled high with a 10K resistor, it it does not need to be connected to the JTAG header in any way?

And the JTAG reset pin should be connected to TRST on the chip correct?

[lpcware]

Content originally posted in LPCWare by Alex on Fri Feb 08 01:25:07 MST 2013
On the LPC4330-Xplorer evaluation/reference board DBGEN is pulled high via a 10 k resistor. I do not see this on your board.

[lpcware]

Content originally posted in LPCWare by Alex on Fri Feb 08 01:22:15 MST 2013
How about DBGEN? You need to pull it to the right level.

Is it RESET or TRST on your JTAG header?
I don't know if the regular RESET pin will work.

Best regards,
Alex

[lpcware]

Content originally posted in LPCWare by avr458 on Thu Feb 07 20:31:32 MST 2013
If you look at the schematic in the zip I attached my 10 pin JTAG header is connected like this:


3.3--|1|2 |--SWIO/TMS
GND--|3|4 |--SWDCLK/TCLK
GND--|5|6 |--SWO/TDO
   --|7|8 |--NC/TDI
GND--|9|10|--Reset


I based my design off the LPC4330-Xplorer evaluation/reference board. What did I do wrong?

[lpcware]

Content originally posted in LPCWare by Alex on Thu Feb 07 01:30:43 MST 2013
Hi avr458,

did you pull DBGEN to the correct level for JTAG or SWD?

Did you connect TRST to the JTAG Interface?

Regards,
Alex