LPC43xxv AHB multilayer matrix and dual Flash bank delays

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by scjames on Sun May 24 17:41:51 MST 2015
I' am working on a dual core application with M4 code in Flash bank A and
M0APP code in bank B.

I some questions regarding devices with dual Flash banks and the AHB Multilayer matrix.

1. I understand that each Flash bank has its own Flash accelerator register FLASHCFGA and FLASHCFGB
Does this imply that each flash bank has its own separate AHB multilayer matrix connection?

2. Are both Flash accelerator access caching logic blocks separate/independent or shared?
i.e. an data cached from previous Flash bank A access; will this get flushed/overwritten by an access to flash bank B?

3. If core A is accessing flash bank A and simultaneously core B accesses flash bank B, will their be any arbitration delays
causing core B to wait for core A or vice-versa?