Content originally posted in LPCWare by yaofree on Wed Oct 22 01:32:59 MST 2014
hi, I meet a SRAM problem.
After writing a byte/word, I can read it ok . But After reading, the byte/word is disappeared and become a zero. In other words, the writed word is disappeard and changed to zero after another read/write opperation.
I am very sad for 2 days for this. :(( . Can anyone help me ?
the SRAM chip is AS4C16M16S (256Mbit/16M * 16bit , 4Mword * 16 bit * 4-bank)
This is my part of SDRAM_Init():
LPC_SCU->EMCDELAYCLK = 0x2222 ; // 3.5 ns EMC clock delay
//Also at higher clock rates you need to change EMCDELAYCLK (I have 0x0000 for up to 96MHz, 0x1111 for 97 to 129MHz and 0x2222 above that).
LPC_EMC->CONTROL = 0x00000001;// reset
LPC_EMC->CONFIG = 0x00000000;
LPC_EMC->DYNAMICCONFIG1 = 0<<14 | 3<<9 | 1<<7; /* 256Mb, 16Mx16, 4 banks, row=13, column=9 */ // yao_todo
pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE);
LPC_EMC->DYNAMICRASCAS1 = 0x00000303; /* 3 RAS, 3 CAS latency */
LPC_EMC->DYNAMICREADCONFIG = 0x00000003; /* Command delayed strategy, using EMCCLKDELAY */
LPC_EMC->DYNAMICRP = NS2CLK(pclk, 20);
LPC_EMC->DYNAMICRAS = NS2CLK(pclk, 60);
LPC_EMC->DYNAMICSREX = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICAPR = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICDAL = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICWR = NS2CLK(pclk, 20);
LPC_EMC->DYNAMICRC = NS2CLK(pclk, 70);
LPC_EMC->DYNAMICRFC = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICXSR = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICRRD = NS2CLK(pclk, 14);
LPC_EMC->DYNAMICMRD = NS2CLK(pclk, 20);//0x00000002;
TIM_Waitus(100); /* wait 100ms */
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
TIM_Waitus(200); /* wait 200ms */
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
LPC_EMC->DYNAMICREFRESH = /*2*/EMC_SDRAM_REFRESH(pclk,70); /* ( n * 16 ) -> 32 clock cycles */
TIM_Waitus(200); /* wait 200ms */
tmpclk = (uint64_t)15625 *(uint64_t)pclk/1000000000/16; //
LPC_EMC->DYNAMICREFRESH = tmpclk;
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
//Timing for 48/60/72MHZ Bus
temp = *((volatile uint32_t *)(SDRAM_ADDR_BASE | (2<<4| 3)<<11)); /* 4 burst, 3 CAS latency */
temp = temp;
LPC_EMC->DYNAMICCONTROL = 0;/* Issue NORMAL command */
LPC_EMC->DYNAMICCONFIG1 |= 1<<19;
