lpcware

LPC4357-EVB + SDRAM

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by hekutoc on Fri Nov 08 06:52:40 MST 2013
Have: LPC4357-EVB dev board  and LPCOpen 1.03 and IAR

CPU Frequency - 204MHz
EMC - divider by 2  so frequency is 102MHz

Have problems with EMC execution in pair with SDRAM (MT48L16M16A2 -75).

I have launched some samples, based on 1.01, where EMC works fine (so there is no hardware problems). After init all register values are equal. Difference only in  MODE recording to SDRAM. But changing shifts to any side (even same, as was in 1.01) doesn't solve the problem.

Still having bery interestig symthomes, that I can't decrypt.
Writing - OK
[img]http://i.imgur.com/nhgATiJ.png[/img]

Reading - strange values
[img]http://i.imgur.com/dhbGB7a.png[/img]

Have few questions:
1) (writing of MODE register) Why it differs and what shift is needed for? Why is it associated with col_num?

//SDRAM_ADDR_BASE = DynAddr = 0x28 000 000
//v1.01  here comment says 4 burst, but  ... |3 ... means 8 burst.
temp = *((volatile uint32_t *)(SDRAM_ADDR_BASE | (3<<4| 3)<<11)); /* 4 burst, 3 CAS latency */
//v1.03 here ModeRegister=51 Col_len=8 or 9
temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len)));

2) What should i cange to make everything work.

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