GPDMA Configuration for SSP/SPI Transfer

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by stanley76726 on Mon Nov 12 06:10:14 MST 2012

I modified the GPDMA example from PDL to support P2M transfer mode. My purpose is that SSP0, as a master, can receive 80-byte data to memory, and now SSP1 is simulated to be the slave to transfer 80-byte data by writing the data register (LPC_SSP1->DR).

One version of this example configured the DMA transfer size as 8 bytes, because of the limitation of SSP/SPI FIFO buffer size (i think so), where means DMA needs to transfer 10 times. However, re-initialization of channel-related registers (channel config/control, channel enabling registers) is so time-consuming that we cannot afford it (300~400us between two DMA transfers), although it works fine.

Therefore, the other version, i reconfigured the transfer size as 80 bytes, and i thought writing 80-byte data to LPC_SSP1->DR directly does never work. Therefore, i had it transfer in DMA M2P mode, hoping that DMA controller can handle this automatically. However, it never starts to transfer at all...

Is it possible for GPDMA controller to transfer 80-byte data from SSP/SPI to memory whenever the FIFO is full or not empty, and to response a terminal count signal while finishing with an interrupt? All of above are done after finishing GPDMA configuration, so that polling to check the SSP FIFO status is unnecessary.

Best Regards,