lpcware

LPC4370 SCT and HSADC

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by hfxiao_cn on Tue Jan 06 17:19:09 MST 2015
Hi,

I have a LPC4370. I am using SCTOUT8 to hardware trigger HSADC.

The CPU clock is: 160MHZ
The SCT clock is:  160MHZ
The HSADC clock is : 80MHZ


CPU Clock, SCT Clock, and HSADC Clock are all generated from Main PLL with 20MHz external crystal. 
So I can assume that the rising edges of these 3 clocks are all lined up.

I use SCTOUT8 to trigger HSADC, i.e., connect SCTOUT8 to HSADC trigger via GIMA:

/* Hardware trigger only, rising external trigger, do not synchronize external trigger input, 0x90 recovery clocks, add channel IF to FIFO entry */
Chip_HSADC_ConfigureTrigger(LPC_ADCHS,
                                                                     HSADC_CONFIG_TRIGGER_EXT,
                                                                     HSADC_CONFIG_TRIGGER_RISEEXT,
                                                                     HSADC_CONFIG_TRIGGER_NOEXTSYNC,
                                                                     HSADC_CHANNEL_ID_EN_ADD, 0x90);


/* Hardware trigger from SCTOUT8 */
LPC_CREG->CREG6 |= (1<<4); //SCT outputs only. SCT outputs are used without timer match outputs.
LPC_GIMA->ADCHS_TRIGGER_IN =  (0x0 << 0 ) | // Not inverted 
                                                               (0x1 << 1 ) | // Rising edge detection enabled
                              (0x1 << 2 ) | // Enable synchronization
              (0x0 << 3)  | // Disable single pulse generation
              (0x7 << 4);   // CTOUT_8

/* Table 0, Descriptor 0 : mapped to input 1, NO Power down after this conversion bit, Branch to the first descriptor, Match time is set to 1, No threshold detection performed, Reset descriptor timer  */
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(1) |
                                                                                                     HSADC_DESC_NOPOWERDOWN |
  HSADC_DESC_BRANCH_FIRST |
                                                                                                     HSADC_DESC_MATCH(1) |
  HSADC_DESC_THRESH_NONE |
                                                                                                     HSADC_DESC_RESET_TIMER));

In my code, I write to SCT control register to start the SCT, and SCTOUT8 will output a 10KHZ PWM. The SCTOUT8 then will trigger HSADC to start the sampling and conversion. I will let SCT running for10us, and then shut down the HSADC and SCT. And Keep this repeated in a while loop.

I am looking at the time delay between SCTOUT8(10KHz PWM) starting point and HSADC trigger point, which I denoted as T_PtoA.

I found that T_PtoA is either (1) or (2):
(1) half HSADC clock cycle + a fixed HSADC trigger latency
(2) one HSADC clock cycle + a fixed HSADC trigger latency

I attched an xlsx file and a pdf file with this post, which has some timing diagram showing what I am talking about the T_PtoA.

In my application, I would like to have a fix T_PtoA. The half HSADC clock cycle difference between (1) and (2) is not good for my application. I want all the T_PtoA to be fixed as (1). Or I want all the T_PtoA to be fixed as (2)

Can anyone help with this issue?

Thanks in advance.




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