lpcware

SPIFI cache and capabilities

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by cb03scs on Tue Oct 21 04:43:03 MST 2014
Currently we are using the LPC4370 for a project and there were some unanswered questions about the SPIFI:

In the User-Manual is the sentence: "Built-in cache to give high-performance code execution."
But how big is the cache really? 8B, 32B, ..., 1kB, ...?
How long is one cache line? 8B, 16B, ...?
What is the clock of the cache? is it the same as the whole SPIFI module or is it clocked with the AHB bus speed?

And some other question regarding the compatibility of the SPIFI module:
Is it compatible with SD-Cards? Could I remove the 4MB Flash on the evaluation board and attach an SD-Card without the need of a special boot loader? (That I'd be unable to access the whole SD-Card at once or even at all is not important to me.)

Are there some Documents on the NXP Homepage that I have not found yet regarding these questions?

If someone could answer these questions that would be terrific...

Thank you

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