GPDMA usage question - ping-pong implementation

[lpcware]

Content originally posted in LPCWare by sfenwick76 on Wed Jun 11 06:23:29 MST 2014
Hello,

I am trying to write a UART driver that uses ping-pong buffers for RX.  I have done this on other processors (STM Cortex M3 for example) by changing the "next" pointer while the DMA is running to swap between 2 buffers so I can read from one while the DMA is writing to the other.  Unfortunately, I found this note in the 43xx datasheet regarding the GPDMA LLI register

from 20.6.18: "Programming this register when the DMA channel is enabled may have unpredictable side effects."

I assume this means I cannot change the "next" pointer while the DMA is running.  Does anyone know how I would implement a ping-pong scheme for UART RX?  Do people have another suggestion for efficient UART RX implementation using DMA?  (Our UART application is a command line interface that will sometimes be driven by a script running on a PC.)

Thanks,
Steve

[lpcware]

Content originally posted in LPCWare by sfenwick76 on Thu Jun 19 13:07:22 MST 2014
Pacman,

Thanks for your help! This makes complete sense.  I have been reading more about the GPDMA and I have some further questions if someone knows.  I can't seem to figure it out from the datasheet.

- Can we still get USART RDA interrupts when USART RX DMA is enabled?  I want to implement a mechanism for unblocking a task when a new character arrives after waiting for a while.  For example, I have a getchar() function which blocks on a semaphore while it is waiting for a new character from USART RX to arrive.  I would like the USART RDA interrupt to be able to trigger the unblocking of the semaphore. 

- In the section regarding DMA Channel Destination Address registers, it says that "Reading the register when the channel is active does not provide useful information". and "It is intended to be read only when a channel has stopped,"  Does this apply to the chain of buffers when using scatter/gather or just the GPDMA register at 0x40002108?  It is still OK to read the value to get a worst-case-scenario (e.g., to tell us there is at least one byte of data in the buffer)?
 
- How do we find out the burst size of the USART peripheral for USART RX?  What would happen if RXTRIGLVL in the USART is set to 14 characters and the DMA burst size is set to 16?  Does the RXTRIGLVL need to be the same as the DMA burst size? 

- Does the USART RX DMA support DMA-driven and USART-driven flow control options?  Or just one?

- What is the difference between SOFTLBREQ and SOFTBREQ?  What does a "last burst" mean?

[lpcware]

Content originally posted in LPCWare by Pacman on Wed Jun 11 14:46:42 MST 2014
I believe you have plenty of options.

Have a look at the DMA-Channel Transfer Completed interrupts.

But imagine you have a LLI at address 0x20002000 and you have another LLI at address 0x20002040.
You can easily change the next-pointer in that memory, if you want to.

I imagine that what you're looking for is a LLI1 pointing to LLI2 and LLI2 pointing back to LLI1, and then using a transfer completed interrupt on each of those LLIs.  ;-)