SGPIO SPI master emulation, bits reversed?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Zuofu on Sat Sep 21 17:52:49 MST 2013

According to AN11210 (SGPIO SPI master emulation) Figure 3 (and almost every schematic of the SPI standard I've seen), data is to be shifted out MSB first. However, from what I can tell from the example code running on a LPC4337, data written using the SGPIO_spiWrite(...) function results in it being shifted out LSB first. This is consistent with the datasheet description of the REGx slice data register, which describes it as being right shifted (LSB first). Of course, the example code is a loopback test, so it would work regardless of whether the LSB or the MSB is shifted first, but clearly this doesn't work for general devices which use the MSB-out first convention.

Is the diagram in the document a mistake, or did I do something wrong? Is there a way to change the shifting behavior of the SGPIO port? I would guess not due to the post referenced here: http://www.lpcware.com/content/forum/reversing-bits-sgpio-output