lpcware

LPC4337 and SSD1963

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Bladerunner_Mike on Sun Jan 26 19:56:02 MST 2014
We've attached SSD1963 based tft dsyplay to EMC (signals: D15..D0 , RD#, WR#, CS#, A2). Dysplay require 8080-like bus for communication. In the 8080-mode interface consist of CS#, D/C#, RD#, WR#, D[16(8,9,24):0]  This interface use WR# to define a write cycle and RD# for read cycle. If the WR# goes low when the CS# signal is low, the data or command will be latched into the
system at the rising edge of WR#. Similarly, the read cycle will start when RD# goes low and end at the
rising edge of RD#. But interval between edges of WR# and CS# is too small, these signals are quite synchronous.

How to increase this interval?


The code of static init is following:

void emcStaticInit ()
{
       
        EMC_STATICWAITWEN0_bit.WAITWEN        = 0xF; //
        EMC_STATICWAITWR0_bit.WAITWR          = 0x1F;
        EMC_STATICWAITOEN0_bit.WAITOEN        = 0xF;
        EMC_STATICWAITPAGE0_bit.WAITPAGE      = 0xf;
        EMC_STATICWAITTURN0_bit.WAITTURN         = 0x1f;
               
      
        EMC_STATICWAITRD0_bit.WAITRD           = 0x1f;
       
        EMC_STATICCONFIG0_bit.B  = 0x0;
       
        EMC_STATICCONFIG0_bit.MW = 0x1;
        EMC_STATICCONFIG0_bit.PM = 0x0;
        EMC_STATICCONFIG0_bit.PB = 0x1;
       

}


In previous project we used GPIO for emulation 8080 bus interface, and initialization code of SSD1963 work well, and we could control diagrams of CS# WR# and D, A.

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