Undocumented error, changing core speed to 204Mhz

[lpcware]

Content originally posted in LPCWare by larsjep on Mon May 14 04:05:03 MST 2012
Hi,

I have some troubles getting a LPC4350, rev A. to run at 204 Mhz.
Some instructions after I have switched to 204Mhz, the processor crashes.

PhilYoung mention that this is a know problem in this thread:
http://www.lpcware.com/content/forum/systemcoreclockupdate

Is there any recommened workaround for this problem ?

Best regards
  Lars

[lpcware]

Content originally posted in LPCWare by larsjep on Tue Jul 03 01:17:28 MST 2012
I'm running on the Hitex Evaluation board.

It doesn't have buffer between the SDRAM and the LPC4300, but there are buffers on the address lines that goes to the SRAM and flash.
Could this be the problem ?

What is your timmings setup for the SDRAM ?

Regards
  Lars

[lpcware]

Content originally posted in LPCWare by PhilYoung on Mon Jul 02 09:27:24 MST 2012
I'm running it fine with external SDRAM using 201.6MHz core clock, and 100.8MHz SDRAM clock.

The only issue that I know kills this is when you use buffers in the address lines to the SDRAM.

Although the timing should not be affected by this it clearly is, the address timing when using the divided clock is tighter.

I experienced exactly this problem with buffers in the address lines, and removing them resolved the problem completely.

regards


Phil.

[lpcware]

Content originally posted in LPCWare by larsjep on Mon Jul 02 07:14:14 MST 2012
Hi again,

I still have serious problems getting my board to run at 204Mhz and execute from SDRAM.

I have tried the different workarounds you proposed, but I can only get it to run stable from internal memory.

When I start to execute from the external memory (SDRAM) it hardfaults very quickly.
If I run at 102Mhz (with EMC div = 1) it run perfectly. But when I run it at 204 Mhz (with EMC div = 2) it crashes.

I have tried to follow the description in the new manual (rev 1.2), but it doesn't really work.
In section 11.2.1.1 it states "Select the M and N divider values to produce a PLL1 output > 110 MHz"
But this is not possible without also changing PSEL, I assume this is just missing from the manual.
But if I just change PSEL, M and N, while running from PLL1 it just crashes.

If I look in the PDL this is also not what is happening.
The function CGU_SetPLL1(...) first programs the PLL1_CTRL to some invalid value (is this a good idea when the core is running from the PLL)
Then a bit later programs the new values to PLL1_CTRL. This works sometimes depending on the time between the 2 writes to PLL1_CTRL. This doesn't really seems to be a reliable way of starting up the processor.

Have anyone tried to run it at 204Mhz and execute from SDRAM ?


Best regards
  Lars

[lpcware]

Content originally posted in LPCWare by usb10185 on Tue Jun 19 12:21:50 MST 2012
It is documented in the latest UM.
http://www.nxp.com/documents/user_manual/UM10503.pdf
See Chapter 11.

[lpcware]

Content originally posted in LPCWare by PhilYoung on Wed May 16 15:51:26 MST 2012
This is an undocumented but known problem,
It's not a PLL problem, but due to the internal voltage regulator.
The trick is to switch the CPU clock first to an intermediate frequency then wait for the PSU to stabilize before switching to a higher frequency.

Since I use PLL0Audio to clock the CPU I set up PLL1 to 150 MHz and PLLAudio to 200 MHz, first I use PLL0Audio / 2 using iDIVA on PLL0Audio, this gets to 100 MHz, then switch to PLL1, then to PLL0Audio, leaving a few ms between each switch.

You can in theory just go to 100 then 200MHz, but this seemed less reliable.

the code is as follows ( excluding the PLL setup code )

   #define CPU_CLK_SRC 8
   SetClkSource(&LPC_CGU->BASE_M4_CLK,0xC);// = (1 << 11) | (8 << 24); // DIVA ( 100.8 MHz)
   Pause(1000);
   SetClkSource(&LPC_CGU->BASE_M4_CLK,0x9);// PLL1 ( 150 MHz)
   Pause(1000);
   SetClkSource(&LPC_CGU->BASE_M4_CLK,CPU_CLK_SRC);// = (1 << 11) | (8 << 24); // PLL0_AUDIO

regards

Phil.

[lpcware]

Content originally posted in LPCWare by nxp21346 on Mon May 14 16:25:16 MST 2012
The clock can't be switched directly from 12 MHz to 204 MHz. Instead, the clock should be switched from 12 MHz to 108 MHz, then there should be a 100 uS delay, and then the PLL can be programmed to go from 108 MHz to 204 MHz. There is an example of this in the peripheral driver library at sw.lpcware.com in the BOOTFAST Example directory.

[lpcware]

Content originally posted in LPCWare by wellsk on Mon May 14 16:12:09 MST 2012

Sorry, I must be out of it today. Somewhere I thought I saw this was a lpc3250 related problem :(
I'll let someone else handle this.

[lpcware]

Content originally posted in LPCWare by larsjep on Mon May 14 14:44:17 MST 2012
I'm not sure what you mean, it is not a 3250, but a 4350 ??

I'm running from internal RAM with a debugger and not using the CMSIS/CDL library.
I use a 12Mhz oscillator. First I configure the core to run from the internal oscillator. Then I setup the PLL1 to multiply by 17.
Waits for it to stabilize.
Then I switch the core clock to PLL1 (204 Mhz).
After a couple of instructions I get a hardfault.

If I singlestep with the debugger it sometimes works and then runs stable at 204 Mhz.


Regards
  Lars

[lpcware]

Content originally posted in LPCWare by wellsk on Mon May 14 09:49:17 MST 2012
The 3250 doesn't use a CMSIS library and the clock setup is different than other parts.
As far as I know, there are no problems with lpc3250 clocking.

Can you give more information about what you are actually seeing? Are you running code from NOR FLASH?