lpcware

Level Sensitive Interrupt Issue

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by VictorValencia on Mon Oct 14 14:54:22 MST 2013
Hi Everyone,

  I am running into an issue using level sensitive interrupts on the LPC 4337.

I have a level-sensistive (low) interrupt configured for a simple gpio interrupt
test.  The trigger pin is direct connected to the interrupt pin.  The intention is to
set the trigger pin low and verify that an interrupt is generated on the "interrupt" pin.

The primary gpio ISR will write the appropriate bit in the PSTAT register to acknowledge
the interrupt but only for edge-triggered interrupts.  According to the reference manual for
level sensitive interrupts a write to PSTAT will reverse the level trigger sense (from low to high) to
disable further interrupts.

So the original code does  this:

<start test>
<trigger gpio pin is set low>
<interrupt occurs on interrupt pin>
<ISR runs>
    if (intType == edge)
        write appropriate bit to PSTAT;
    set the trigger pin high;
<test complete>

What I am finding is that if the ISR does not write PSTAT (due to int not being edge triggered)
and only sets the trigger pin high the interrupt keeps firing.  Since the trigger pin becomes
high the interrupt condition is not present and the interrupts should stop.  If I instead change
the code to unconditionally write the PSTAT register (regardless of interrupt type) everything
works fine (just get one interrupt).

It acts as if setting the trigger pin low does not stop the interrupt from firing.  If I change the code
to unconditionally write the PSTAT (regardless of interrupt type) then there might be the unintended
consequence that a subsequent change of the trigger pin to a high state will generate another interrupt.

The fundamental question is why doesn't removing the interrupt condition by itself stop interrupts from
occurring?

Any ideas on why this is happening? 

Victor

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