Does LPC4300 works with 32MB SDRAM?

[lpcware]

Content originally posted in LPCWare by irvin on Wed May 16 01:24:49 MST 2012
Can anybody confirm that LPC43xx works with following 32MB SDRAM parts: ISSI IS45S32800D or Micron MT48LC8M32LF?

On our board we use 256Mb SDRAM which have: 8M x 32b (Row length:12, Column length: 9, Bank: 4) configuration.

According to the user manual (DYNAMICCONFIG register), this SDRAM configuration is not supported. I spoked with NXP, and they told me to use following register settings (shown in user manual, table 364 - see attachment):
32 external bus high-performance address mapping
- 128 Mb (8Mx16), 4 banks, row length = 12, column length = 9

Unfortunately it does not work for us. Currently we use settings
- 128 Mb (4Mx32), 4 banks, row length = 12, column length = 8,
but only 16MB work.

Does anyone use same SDRAM, and can provide me DYNAMICCONFIG register settings?

[lpcware]

Content originally posted in LPCWare by Prabhakaran_Raja on Mon Feb 22 21:21:25 MST 2016
Thanks,

I'm using LPCXpresso v7.9.2 IDE.
For LPCXpresso IDE don't have any SDRAM examples in the above link. (Only Keil have it.)
Please suggest an example of LPC4357 xplorer++ evl board SDRAM interface.

[moller]

Did you ever find an example for SDRAM with proper config files? I am having a hard time interfacing with my 64 MB SDRAM block.

[lpcware]

Content originally posted in LPCWare by mc on Mon Feb 22 11:12:12 MST 2016
Hi,
If you have LPClink you can not use it with Keil. If you have LPCLink2 you can use it with keil. You need to prgram it in CMSIS DAP mode.
https://www.lpcware.com/lpclink2

You can convert .axf into .hex and use Flashmagic to program it. Download FlashMagic from
http://www.flashmagictool.com/

You can find SDRAM example using LPCXpresso in LPCOpen S/W package. See here
https://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc43xx-packages

[lpcware]

Content originally posted in LPCWare by Prabhakaran_Raja on Thu Feb 18 07:18:53 MST 2016

Hi,
I have LPC4357 xplorer++ evl board and NXP LPC-Link debugger.
i using LPCXpresso v7.9.2 IDE.
In my evl board we have MT48LC8M32B2B5-6 SDRAM.
but i'm trying to interface SDRAM in all the way but i'm not able to interface with SDRAM.
some keil examples are there but i cannot flash the *.afx through LPC-Link .

Please any one suggest how flash using LPC-Link with keil examples?
AND please suggest any direct example of SDRAM interface using LPCXpresso v7.9.2 IDE.

[lpcware]

Content originally posted in LPCWare by ehughes on Sat Feb 06 12:57:33 MST 2016
I have used the 64Megabyte device and have verified it to be working.

[lpcware]

Content originally posted in LPCWare by kralux on Sun Sep 01 19:43:28 MST 2013
Can you please confirm that you can actually access all 32 MBytes? Because doing the same thing with the same chip, we can only access the first 16 MBytes. What the NXP guys told you at first makes sense from that point of view.

[lpcware]

Content originally posted in LPCWare by irvin on Fri May 18 03:57:11 MST 2012
It works!

With your register suggestions, 13bit sift (RBC), it started to work for the first time. We didn't pay attention on 13bit shift for mode register, before. Thanks!

Regards,
Irvin

[lpcware]

Content originally posted in LPCWare by PhilYoung on Fri May 18 01:32:41 MST 2012
reading the data sheet in more detail it appears it shouldn't support this configuration since all values not in the table are reserved, and selecting 128Mb part will not drive the upper address bit of the row address.
there is not a direct correlation between the AM0 / AM1 settings and the number of address bits, see note 1 on page 416.

AM1 clearly selects 32 bit mode, but it seems that the address shifts are a hard coded function of AM0.

I guess though you could try telling it that there are 2 devices of 16M * 16 as I believe it only ever performs 32 bit accesses in 32 bit mode.

In this case try the settings
1 0 011 01 256 Mb (16Mx16), 4 banks, row length = 13, column length = 9

then as collum length is 9, you will need to use a left shift of 11 for BRC and 13 for RBC mode when loading the mode register.

regards

Phil.

[lpcware]

Content originally posted in LPCWare by irvin on Thu May 17 12:41:10 MST 2012
I also used 64Mb SDRAM with LPC2468 and LPC1778 without any problems. Now on Cortex M4 platform we decide to go with bigger one. You can see bellow my routine for SDRAM mode register initialization. Frankly, i don't see relation between possible register values and partial visibility of SDRAM.

#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))

LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
WR_MODE(((3 << 4) | 2) << 12);
WaitUs (10);
LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */

[lpcware]

Content originally posted in LPCWare by PhilYoung on Wed May 16 16:03:46 MST 2012
I've used both the MT48LC4M32B2 and MT48LC8M16A2 parts which seem fine, so I can't see any reason that these parts will not work.
If you are only able to access half of the SDRAM then it sounds like you are not programming the correct values into the SDRAM rather than the SDRAM controller.

for the 32 bit SDRAM I use the following for loading the SDRAM's mode register for the 32 bit devices.

        volatile unsigned gNULL;


if(ROW_BANK_COLLUMN){
                gNULL = *((volatile unsigned *)(0x28000000 | ((0x02 | (CAS_Latency << 4)) << 12)));
} else {
gNULL = *((volatile unsigned *)(0x28000000 | ((0x02 | (CAS_Latency << 4)) << 10))); // BL = 4, CL = 3
}


note that I use a global volatile unsigned as the target for the result so that the code can be safely compiled at all optimization levels, otherwise it may get removed and the memory won't work.

regards

Phil