Content originally posted in LPCWare by bavarian on Mon May 23 02:47:02 MST 2016
The USB0 block is an AHB master, but not the only one on this bus. So if you have various things running the bus will be shared and transfers might be delayed due to bus contentions.
Have a look at Fig. 12 and 13 in the user manual to see the different bus connections for the different components in the LPC4300. It's not easy to say what could be the most effective setup, but if you start thinking from a bad setup, then you might get an idea how to do it better:
Bad setup: variables and stack/heap in 0x10000000 SRAM area, buffers for USB0 in the same memory area.
This means that the DMA fetching from the buffer gets all the time in conflict with Cortex-M4 accesses for parameters and stack/heap.
Can you also check if the register USB0.SBUSCFG is set to 3 by your software. If not, then the internal buses don’t work fine in case of bulk transfers.
Regards,
NXP Support Team