LPC43xx HS USB Speed

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LPC43xx HS USB Speed

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by damihuang on Sun May 15 22:52:01 MST 2016
Hi,

Anyone tried to push LPC43xx's HS USB transfer speed to limit? We are using LPC43xx to build a realtime data logger that require 40MB/s transfer speed from LPC43xx to PC. But everything we tried only get 16MB/s. Anyone has any experience on this?

Frank
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lpcware
NXP Employee
NXP Employee
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by damihuang on Thu May 26 23:41:53 MST 2016
Hi,

I use the keil 4.74,and I find the register SBUSCFG in the latest docs .But I set the register vaule to 3, it doesn't work better.

I have no ideas about the bad setup ,could you tell me more details?

Thank you.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by lpcxpresso-support on Thu May 26 02:13:43 MST 2016
Hi,

Take a look at:

http://www.nxp.com/documents/user_manual/UM10430.pdf

This register is described (it would appear to be a later arrival to the docs).

Yours,

LPCXpresso-support
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by damihuang on Tue May 24 18:13:08 MST 2016
Hi

The buffers for USB0 and program are in the same SRAM area, and I have not find the register USB0.SBUSCFG.

Thank you.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by bavarian on Mon May 23 02:47:02 MST 2016
The USB0 block is an AHB master, but not the only one on this bus. So if you have various things running the bus will be shared and transfers might be delayed due to bus contentions.
Have a look at Fig. 12 and 13 in the user manual to see the different bus connections for the different components in the LPC4300. It's not easy to say what could be the most effective setup, but if you start thinking from a bad setup, then you might get an idea how to do it better:

Bad setup:  variables and stack/heap in 0x10000000 SRAM area, buffers for USB0 in the same memory area.

This means that the DMA fetching from the buffer gets all the time in conflict with Cortex-M4 accesses for parameters and stack/heap.

Can you also check if the register USB0.SBUSCFG is set to 3 by your software. If not, then the internal buses don’t work fine in case of bulk transfers.

Regards,
NXP Support Team
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by rocketdawg on Mon May 16 08:07:34 MST 2016
Not possible since the effective rate is only 35MB/s.  And even then, it depends on the OS and the capabilities of the PC (high end I7)
you might want to look at the open souce for
http://www.embeddedartists.com/products/app/labtool.php

I think they are running USB about as fast as it will go.
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