LPC4350 SSP0 SPI Slave mode problem

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LPC4350 SSP0 SPI Slave mode problem

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Abrams on Fri May 06 08:23:57 MST 2016
Hi,

I'm using LPC4350 as Slave on SPI. In debug mode, when a packet is sent to Slave nothing happens neither an interrupt nor flag setting in SSP0 Status Register. Data in Data Register is 0x0000 also.

I changed SPI mode to Master and tried to send some data. I found that SSP0 operates and sends data as Master, but in Slave it does not.

Has Master to raise SS line for SSP0 module at each 8-bit transfer? In my case Master keeps SS line low during 12-bytes transmission.

SPI frequency is 160 kHz.

Is there a code example for configuring SSPx as SPI Slave?


Thanks.
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lpcware
NXP Employee
NXP Employee
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Abrams on Fri May 06 09:37:27 MST 2016
I'm aware about SPI.

That's amazing. Enabling EZI made SPI Slave operating.
Many thanks!
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by mysepp on Fri May 06 09:07:58 MST 2016
PS: Have a look at https://de.wikipedia.org/wiki/Serial_Peripheral_Interface
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by mysepp on Fri May 06 09:07:02 MST 2016
Have you used SPI/SSP before, perhaps with a different controller, or is it the first time you are using it?
The master generates clocks, the slave receives this clock.
Only when the slave is selected by a CS (chips select=SS=SSEL), it is allowed to send data back.
It is usually a good thing (saves you some time to analyse, why it is not working as you want),
when you configure CS=SS=SSEL as GPIO and control it by yourself, instead of let SSP/SPI let control it automatically.
BTW: The clock of Master occurs only, when data is sent and only the amount of 2 transitions each bit.
After the transfers the clk remains stable at a certain level.
Pay attention to EZI bit, which enables the receiver. Otherwise you get only 0xFF.
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