Content originally posted in LPCWare by mysepp on Fri May 06 09:07:02 MST 2016
Have you used SPI/SSP before, perhaps with a different controller, or is it the first time you are using it?
The master generates clocks, the slave receives this clock.
Only when the slave is selected by a CS (chips select=SS=SSEL), it is allowed to send data back.
It is usually a good thing (saves you some time to analyse, why it is not working as you want),
when you configure CS=SS=SSEL as GPIO and control it by yourself, instead of let SSP/SPI let control it automatically.
BTW: The clock of Master occurs only, when data is sent and only the amount of 2 transitions each bit.
After the transfers the clk remains stable at a certain level.
Pay attention to EZI bit, which enables the receiver. Otherwise you get only 0xFF.