lpcware

4 x SDRAM at LPC43x7

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by khfreiberg on Mon Dec 02 16:23:12 MST 2013
Hi,
I have 4 x MT48LC64M8A2 (-75) at dynCS1 to use the full 256MB. It is a brand new prototype board.
EMC is running at 204/2MHz. I have problems with the setup. My little RAM test works fine at first run. But when I read the data again they change. The changed data seems to be stable with a '00' in chip 1 and 'FF' in chip 2. Other data are shifted by 4 byte in address. Looks like a refresh issue. I would like to distinguish between layout problem and setup failure. But when I search examples and forum entries it seems like everybody has it's own magic. Especially strange is the multiple calling of 'LPC_EMC->DYNAMICREFRESH' where the shown values doesn't match 'UM10503'. Additionally I am not sure how to calculate the offset for WR_MODE (12?, 14?) for 4 chips. Both values don't change behavior. Does anybody have a working setup that I can use as platform for further investigations?
I would appreciate any help.

Greetings

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