SDRAM with EMC on LPC4370

[lpcware]

Content originally posted in LPCWare by inspire on Mon Oct 12 12:46:53 MST 2015
Hi,

I want to use a LPC4370 with EMC and a SDRAM but I'm not sure about the connection of the address pins. A screenshot is attached.
Is it correct to use A13 and A14 for the bank addresses although the normal address pins only count to 10? Or should I use A11 and A12 for the bank address?

Thanks!
inspire

[victor_gerardin]

Hi,

I want to use an LPC4370 with Samsung SDRAM by EMC, and I was wondering if the power supplies should be provided by the same LDO ? 

I would like to put a 3.3V regulator for the LPC, and another 3.3V regulator for the SDRAM, is this a problem?

Thank's

Victor

[lpcware]

Content originally posted in LPCWare by mc on Fri Oct 16 14:42:00 MST 2015
Hi inspire,
For LPC4300 Maximum SDRAM clock can not be higher than 120MHz. So you have two options
1) Run Core(Cortex M4) at 204 MHz and EMC(SDRAM) at 102 MHZ
2) Run Core(Cortex M4) at 120MHz and EMC(SDRAM) at 120MHz

[hmyoong]

Hi inspire

Could you share with me your experience in interfacing sdram with lpc4370 at high speed? I am working on it too.

[lpcware]

Content originally posted in LPCWare by inspire on Fri Oct 16 13:25:03 MST 2015
Thanks, mc!

One more question came to my mind when I wanted to select a specific SDRAM.

In the LPC4370 datasheet it says "SDRAM clock can run at full or half the Cortex-M4 core frequency". But in different shops I couldn't find SDRAMs that run with 204 MHz. The maximum I could find was 200 MHz for the SDRAM's maximum clock frequency. Do I have to lower the LPC clock frequency to 200 MHz to make the SDRAM run on full speed or what is meant with the quoted sentence?

inspire

[lpcware]

Content originally posted in LPCWare by mc on Tue Oct 13 06:54:30 MST 2015
Hi inspire,
Yes, that is correct. You should connect A13 and A14 to BA0 and BA1.

[lpcware]

Content originally posted in LPCWare by inspire on Tue Oct 13 01:27:53 MST 2015
Hi,
thanks a lot!

I had a look at the app note for the LPC43xx but I couldn't find any information. In one of the other app notes I found the sentence that even if less than 12 address lines are used, still A13 and A14 must be used for bank select.

Have a nice day!
inspire

[lpcware]

Content originally posted in LPCWare by briching on Mon Oct 12 22:06:42 MST 2015
Does this help?  (AN11508)

(http://www.nxp.com/documents/application_note/AN11508.pdf)

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Oct 12 17:17:29 MST 2015
The documentation for physical integration of SDRAM address lines seems to be univerally confusing in the NXP manuals!
We had to redesign our board because of that.

NB: We use 1778 so please double check with the relevant UM.

As far as I know, A13 and (for 4 banks) A14 are always used for the bank select lines and A0 to A??
(depending on the columns on the actual device) for row and column addressing.

See these app notes for better understanding (they are for different families, but are probably the same EMC peripheral?).

A10771, A10935, and AN10950.

For what it is worth, I attach our setup. Using two 16-bit wide devices to get a 32-bit wide memory interface. [32 MB]

Cheers, Mike.